From c02c39fad02c386f6e687e28282973f580fc95ac Mon Sep 17 00:00:00 2001
From: "Cui,Lili" <lili.cui@intel.com>
Date: Mon, 12 Apr 2021 09:59:25 +0800
Subject: [PATCH] Add rocketlake to gcc.

gcc/
	* common/config/i386/cpuinfo.h (get_intel_cpu): Handle
	rocketlake.
	* common/config/i386/i386-common.c (processor_names): Add
	rocketlake.
	(processor_alias_table): Add rocketlake.
	* common/config/i386/i386-cpuinfo.h (processor_subtypes): Add
	INTEL_COREI7_ROCKETLAKE.
	* config.gcc: Add -march=rocketlake.
	* config/i386/i386-c.c (ix86_target_macros_internal): Handle
	rocketlake.
	* config/i386/i386-options.c (m_ROCKETLAKE)  : Define.
	(processor_cost_table): Add rocketlake cost.
	* config/i386/i386.h (ix86_size_cost) : Define
	TARGET_ROCKETLAKE.
	(processor_type) : Add PROCESSOR_ROCKETLAKE.
	(PTA_ROCKETLAKE): Ditto.
	* doc/extend.texi: Add rocketlake.
	* doc/invoke.texi: Add rocketlake.

gcc/testsuite/
	* gcc.target/i386/funcspec-56.inc: Handle new march.
	* g++.target/i386/mv16.C: Handle new march
---
 gcc/common/config/i386/cpuinfo.h              | 10 ++++++++--
 gcc/common/config/i386/i386-common.c          |  4 ++++
 gcc/common/config/i386/i386-cpuinfo.h         |  1 +
 gcc/config.gcc                                |  2 +-
 gcc/config/i386/i386-c.c                      |  7 +++++++
 gcc/config/i386/i386-options.c                |  5 ++++-
 gcc/config/i386/i386.h                        |  3 +++
 gcc/doc/extend.texi                           |  3 +++
 gcc/doc/invoke.texi                           |  8 ++++++++
 gcc/testsuite/g++.target/i386/mv16.C          |  6 ++++++
 gcc/testsuite/gcc.target/i386/funcspec-56.inc |  1 +
 11 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index c1ee7a1..458f41d 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -404,14 +404,20 @@ get_intel_cpu (struct __processor_model *cpu_model,
     case 0xa5:
     case 0xa6:
       /* Comet Lake.  */
-    case 0xa7:
-      /* Rocket Lake.  */
       cpu = "skylake";
       CHECK___builtin_cpu_is ("corei7");
       CHECK___builtin_cpu_is ("skylake");
       cpu_model->__cpu_type = INTEL_COREI7;
       cpu_model->__cpu_subtype = INTEL_COREI7_SKYLAKE;
       break;
+    case 0xa7:
+      /* Rocket Lake.  */
+      cpu = "rocketlake";
+      CHECK___builtin_cpu_is ("corei7");
+      CHECK___builtin_cpu_is ("rocketlake");
+      cpu_model->__cpu_type = INTEL_COREI7;
+      cpu_model->__cpu_subtype = INTEL_COREI7_ROCKETLAKE;
+      break;
     case 0x55:
       CHECK___builtin_cpu_is ("corei7");
       cpu_model->__cpu_type = INTEL_COREI7;
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index b89183b..1e6c159 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -1743,6 +1743,7 @@ const char *const processor_names[] =
   "skylake-avx512",
   "cannonlake",
   "icelake-client",
+  "rocketlake",
   "icelake-server",
   "cascadelake",
   "tigerlake",
@@ -1845,6 +1846,9 @@ const pta processor_alias_table[] =
   {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
     PTA_ICELAKE_CLIENT,
     M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
+  {"rocketlake", PROCESSOR_ROCKETLAKE, CPU_HASWELL,
+    PTA_ROCKETLAKE,
+    M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), P_PROC_AVX512F},
   {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
     PTA_ICELAKE_SERVER,
     M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
index 869115c..e68dd65 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -88,6 +88,7 @@ enum processor_subtypes
   INTEL_COREI7_SAPPHIRERAPIDS,
   INTEL_COREI7_ALDERLAKE,
   AMDFAM19H_ZNVER3,
+  INTEL_COREI7_ROCKETLAKE,
   CPU_SUBTYPE_MAX
 };
 
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 997a9f6..357b0be 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -677,7 +677,7 @@ opteron-sse3 nocona core2 corei7 corei7-avx core-avx-i core-avx2 atom \
 slm nehalem westmere sandybridge ivybridge haswell broadwell bonnell \
 silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \
 skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \
-sapphirerapids alderlake eden-x2 nano nano-1000 nano-2000 nano-3000 \
+sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \
 nano-x2 eden-x4 nano-x4 x86-64 x86-64-v2 x86-64-v3 x86-64-v4 native"
 
 # Additional x86 processors supported by --with-cpu=.  Each processor
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index ed4b098..be46d05 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -242,6 +242,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
       def_or_undef (parse_in, "__alderlake");
       def_or_undef (parse_in, "__alderlake__");
       break;
+    case PROCESSOR_ROCKETLAKE:
+      def_or_undef (parse_in, "__rocketlake");
+      def_or_undef (parse_in, "__rocketlake__");
+      break;
     /* use PROCESSOR_max to not set/unset the arch macro.  */
     case PROCESSOR_max:
       break;
@@ -405,6 +409,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     case PROCESSOR_ALDERLAKE:
       def_or_undef (parse_in, "__tune_alderlake__");
       break;
+    case PROCESSOR_ROCKETLAKE:
+      def_or_undef (parse_in, "__tune_rocketlake__");
+      break;
     case PROCESSOR_INTEL:
     case PROCESSOR_GENERIC:
       break;
diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c
index 02e9c97..91da284 100644
--- a/gcc/config/i386/i386-options.c
+++ b/gcc/config/i386/i386-options.c
@@ -126,9 +126,11 @@ along with GCC; see the file COPYING3.  If not see
 #define m_COOPERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_COOPERLAKE)
 #define m_SAPPHIRERAPIDS (HOST_WIDE_INT_1U<<PROCESSOR_SAPPHIRERAPIDS)
 #define m_ALDERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_ALDERLAKE)
+#define m_ROCKETLAKE (HOST_WIDE_INT_1U<<PROCESSOR_ROCKETLAKE)
 #define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \
 		       | m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE \
-		       | m_TIGERLAKE | m_COOPERLAKE | m_SAPPHIRERAPIDS)
+		       | m_TIGERLAKE | m_COOPERLAKE | m_SAPPHIRERAPIDS \
+		       | m_ROCKETLAKE)
 #define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_ALDERLAKE | m_CORE_AVX512)
 #define m_CORE_ALL (m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE | m_CORE_AVX2)
 #define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
@@ -724,6 +726,7 @@ static const struct processor_costs *processor_cost_table[] =
   &icelake_cost,
   &icelake_cost,
   &icelake_cost,
+  &icelake_cost,
   &skylake_cost,
   &icelake_cost,
   &skylake_cost,
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 24894b4..fab1b3c 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -473,6 +473,7 @@ extern const struct processor_costs ix86_size_cost;
 #define TARGET_COOPERLAKE (ix86_tune == PROCESSOR_COOPERLAKE)
 #define TARGET_SAPPHIRERAPIDS (ix86_tune == PROCESSOR_SAPPHIRERAPIDS)
 #define TARGET_ALDERLAKE (ix86_tune == PROCESSOR_ALDERLAKE)
+#define TARGET_ROCKETLAKE (ix86_tune == PROCESSOR_ROCKETLAKE)
 #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
@@ -2386,6 +2387,7 @@ enum processor_type
   PROCESSOR_COOPERLAKE,
   PROCESSOR_SAPPHIRERAPIDS,
   PROCESSOR_ALDERLAKE,
+  PROCESSOR_ROCKETLAKE,
   PROCESSOR_INTEL,
   PROCESSOR_GEODE,
   PROCESSOR_K6,
@@ -2539,6 +2541,7 @@ constexpr wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
 constexpr wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
   | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
   | PTA_RDPID | PTA_AVX512VPOPCNTDQ;
+constexpr wide_int_bitmask PTA_ROCKETLAKE = PTA_ICELAKE_CLIENT & ~PTA_SGX;
 constexpr wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT
   | PTA_PCONFIG | PTA_WBNOINVD | PTA_CLWB;
 constexpr wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 849c880..e28e186 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -23046,6 +23046,9 @@ Intel Core i7 sapphirerapids CPU.
 @item alderlake
 Intel Core i7 Alderlake CPU.
 
+@item rocketlake
+Intel Core i7 Rocketlake CPU.
+
 @item bonnell
 Intel Atom Bonnell CPU.
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6b585ce..1755124 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -30194,6 +30194,14 @@ MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
 PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL and AVX-VNNI
 instruction set support.
 
+@item rocketlake
+Intel Rocketlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
+SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
+AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
+AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
+
 @item k6
 AMD K6 CPU with MMX instruction set support.
 
diff --git a/gcc/testsuite/g++.target/i386/mv16.C b/gcc/testsuite/g++.target/i386/mv16.C
index 9b29a1a..6839287 100644
--- a/gcc/testsuite/g++.target/i386/mv16.C
+++ b/gcc/testsuite/g++.target/i386/mv16.C
@@ -88,6 +88,10 @@ int __attribute__ ((target("arch=alderlake"))) foo () {
   return 23;
 }
 
+int __attribute__ ((target("arch=rocketlake"))) foo () {
+  return 24;
+}
+
 int main ()
 {
   int val = foo ();
@@ -124,6 +128,8 @@ int main ()
     assert (val == 22);
   else if (__builtin_cpu_is ("alderlake"))
     assert (val == 23);
+  else if (__builtin_cpu_is ("rocketlake"))
+    assert (val == 24);
   else
     assert (val == 0);
 
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 5d4800f..79265c7 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -181,6 +181,7 @@ extern void test_arch_tigerlake (void)          __attribute__((__target__("arch=
 extern void test_arch_cooperlake (void)         __attribute__((__target__("arch=cooperlake")));
 extern void test_arch_sapphirerapids (void)	__attribute__((__target__("arch=sapphirerapids")));
 extern void test_arch_alderlake (void)          __attribute__((__target__("arch=alderlake")));
+extern void test_arch_rocketlake (void)         __attribute__((__target__("arch=rocketlake")));
 extern void test_arch_k8 (void)			__attribute__((__target__("arch=k8")));
 extern void test_arch_k8_sse3 (void)		__attribute__((__target__("arch=k8-sse3")));
 extern void test_arch_opteron (void)		__attribute__((__target__("arch=opteron")));
-- 
2.7.4