From bfc992e2a8d49188d437490c6c022d7eb132617a Mon Sep 17 00:00:00 2001 From: Tanner Gooding Date: Thu, 28 Dec 2017 17:27:49 -0800 Subject: [PATCH] Adding support for the SSE Add, Divide, Max, Min, Move, Multiply, and Subtract scalar intrinsics --- src/jit/hwintrinsiccodegenxarch.cpp | 42 +++++++++++++++++++++++++++++++++++++ src/jit/hwintrinsicxarch.cpp | 7 +++++++ 2 files changed, 49 insertions(+) diff --git a/src/jit/hwintrinsiccodegenxarch.cpp b/src/jit/hwintrinsiccodegenxarch.cpp index 3db92af..4fcb00b 100644 --- a/src/jit/hwintrinsiccodegenxarch.cpp +++ b/src/jit/hwintrinsiccodegenxarch.cpp @@ -222,6 +222,12 @@ void CodeGen::genSSEIntrinsic(GenTreeHWIntrinsic* node) break; } + case NI_SSE_AddScalar: + assert(baseType == TYP_FLOAT); + op2Reg = op2->gtRegNum; + emit->emitIns_SIMD_R_R_R(INS_addss, targetReg, op1Reg, op2Reg, TYP_SIMD16); + break; + case NI_SSE_And: assert(baseType == TYP_FLOAT); op2Reg = op2->gtRegNum; @@ -292,18 +298,36 @@ void CodeGen::genSSEIntrinsic(GenTreeHWIntrinsic* node) emit->emitIns_SIMD_R_R_R(INS_divps, targetReg, op1Reg, op2Reg, TYP_SIMD16); break; + case NI_SSE_DivideScalar: + assert(baseType == TYP_FLOAT); + op2Reg = op2->gtRegNum; + emit->emitIns_SIMD_R_R_R(INS_divss, targetReg, op1Reg, op2Reg, TYP_SIMD16); + break; + case NI_SSE_Max: assert(baseType == TYP_FLOAT); op2Reg = op2->gtRegNum; emit->emitIns_SIMD_R_R_R(INS_maxps, targetReg, op1Reg, op2Reg, TYP_SIMD16); break; + case NI_SSE_MaxScalar: + assert(baseType == TYP_FLOAT); + op2Reg = op2->gtRegNum; + emit->emitIns_SIMD_R_R_R(INS_maxss, targetReg, op1Reg, op2Reg, TYP_SIMD16); + break; + case NI_SSE_Min: assert(baseType == TYP_FLOAT); op2Reg = op2->gtRegNum; emit->emitIns_SIMD_R_R_R(INS_minps, targetReg, op1Reg, op2Reg, TYP_SIMD16); break; + case NI_SSE_MinScalar: + assert(baseType == TYP_FLOAT); + op2Reg = op2->gtRegNum; + emit->emitIns_SIMD_R_R_R(INS_minss, targetReg, op1Reg, op2Reg, TYP_SIMD16); + break; + case NI_SSE_MoveHighToLow: assert(baseType == TYP_FLOAT); op2Reg = op2->gtRegNum; @@ -316,12 +340,24 @@ void CodeGen::genSSEIntrinsic(GenTreeHWIntrinsic* node) emit->emitIns_SIMD_R_R_R(INS_movlhps, targetReg, op1Reg, op2Reg, TYP_SIMD16); break; + case NI_SSE_MoveScalar: + assert(baseType == TYP_FLOAT); + op2Reg = op2->gtRegNum; + emit->emitIns_SIMD_R_R_R(INS_movss, targetReg, op1Reg, op2Reg, TYP_SIMD16); + break; + case NI_SSE_Multiply: assert(baseType == TYP_FLOAT); op2Reg = op2->gtRegNum; emit->emitIns_SIMD_R_R_R(INS_mulps, targetReg, op1Reg, op2Reg, TYP_SIMD16); break; + case NI_SSE_MultiplyScalar: + assert(baseType == TYP_FLOAT); + op2Reg = op2->gtRegNum; + emit->emitIns_SIMD_R_R_R(INS_mulss, targetReg, op1Reg, op2Reg, TYP_SIMD16); + break; + case NI_SSE_Or: assert(baseType == TYP_FLOAT); op2Reg = op2->gtRegNum; @@ -462,6 +498,12 @@ void CodeGen::genSSEIntrinsic(GenTreeHWIntrinsic* node) emit->emitIns_SIMD_R_R_R(INS_subps, targetReg, op1Reg, op2Reg, TYP_SIMD16); break; + case NI_SSE_SubtractScalar: + assert(baseType == TYP_FLOAT); + op2Reg = op2->gtRegNum; + emit->emitIns_SIMD_R_R_R(INS_subss, targetReg, op1Reg, op2Reg, TYP_SIMD16); + break; + case NI_SSE_UnpackHigh: assert(baseType == TYP_FLOAT); op2Reg = op2->gtRegNum; diff --git a/src/jit/hwintrinsicxarch.cpp b/src/jit/hwintrinsicxarch.cpp index 4dfc9a8..7959956 100644 --- a/src/jit/hwintrinsicxarch.cpp +++ b/src/jit/hwintrinsicxarch.cpp @@ -521,6 +521,7 @@ GenTree* Compiler::impSSEIntrinsic(NamedIntrinsic intrinsic, } case NI_SSE_Add: + case NI_SSE_AddScalar: case NI_SSE_And: case NI_SSE_AndNot: case NI_SSE_CompareEqual: @@ -536,13 +537,19 @@ GenTree* Compiler::impSSEIntrinsic(NamedIntrinsic intrinsic, case NI_SSE_CompareOrdered: case NI_SSE_CompareUnordered: case NI_SSE_Divide: + case NI_SSE_DivideScalar: case NI_SSE_Max: + case NI_SSE_MaxScalar: case NI_SSE_Min: + case NI_SSE_MinScalar: case NI_SSE_MoveHighToLow: case NI_SSE_MoveLowToHigh: + case NI_SSE_MoveScalar: case NI_SSE_Multiply: + case NI_SSE_MultiplyScalar: case NI_SSE_Or: case NI_SSE_Subtract: + case NI_SSE_SubtractScalar: case NI_SSE_UnpackHigh: case NI_SSE_UnpackLow: case NI_SSE_Xor: -- 2.7.4