From bfc961aeb2d0e5a05bca7a894cbc4370f5e79a6a Mon Sep 17 00:00:00 2001 From: Sven van Haastregt Date: Wed, 21 Oct 2020 11:46:55 +0100 Subject: [PATCH] [TargetLowering] Check boolean content when folding bit compare Updates an optimization that relies on boolean contents being either 0 or 1 to properly check for this before triggering. The following: (X & 8) != 0 --> (X & 8) >> 3 Produces unexpected results when a boolean 'true' value is represented by negative one. Patch by Erik Hogeman. Differential Revision: https://reviews.llvm.org/D89390 --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 3 ++- llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll | 8 +++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 3e6c11a..bc81d0d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -3981,7 +3981,8 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, EVT ShValTy = N0.getValueType(); // Fold bit comparisons when we can. - if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && + if (getBooleanContents(N0.getValueType()) == ZeroOrOneBooleanContent && + (Cond == ISD::SETEQ || Cond == ISD::SETNE) && (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) && N0.getOpcode() == ISD::AND) { if (auto *AndRHS = dyn_cast(N0.getOperand(1))) { diff --git a/llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll b/llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll index 13e35d9..45701df 100644 --- a/llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll +++ b/llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll @@ -3,8 +3,14 @@ ; Tests the following pattern: ; (X & 8) != 0 --> (X & 8) >> 3 +; This produces incorrect code when boolean false is represented +; as a negative one, and this test checks that the transform is +; not triggered. + ; CHECK-LABEL: @pow2_mask_cmp -; CHECK: bfe.u32 {{%r[0-9]+}}, {{%r[0-9]+}}, 3, 1 +; CHECK: and.b32 [[AND:%r[0-9]+]], %r{{[0-9]+}}, 8 +; CHECK: setp.ne.s32 [[SETP:%p[0-9+]]], [[AND]], 0 +; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, [[SETP]] define i32 @pow2_mask_cmp(i32 %x) { %a = and i32 %x, 8 %cmp = icmp ne i32 %a, 0 -- 2.7.4