From bf6f82a9df6a1693a5399039dcadd7fc00dab65e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 26 Nov 2022 10:07:04 -0500 Subject: [PATCH] StructurizeCFG: Convert tests to opaque pointers --- .../StructurizeCFG/AMDGPU/backedge-id-bug-xfail.ll | 16 ++++++------ .../StructurizeCFG/AMDGPU/backedge-id-bug.ll | 30 +++++++++++----------- .../AMDGPU/loop-subregion-misordered.ll | 30 +++++++++++----------- .../StructurizeCFG/AMDGPU/uniform-regions.ll | 4 +-- .../StructurizeCFG/branch-on-argument.ll | 12 ++++----- .../Transforms/StructurizeCFG/infinite-loop.ll | 16 ++++++------ .../Transforms/StructurizeCFG/invert-condition.ll | 8 +++--- .../StructurizeCFG/invert-constantexpr.ll | 10 ++++---- .../StructurizeCFG/loop-multiple-exits.ll | 10 ++++---- .../Transforms/StructurizeCFG/nested-loop-order.ll | 4 +-- .../StructurizeCFG/one-loop-multiple-backedges.ll | 6 ++--- .../StructurizeCFG/post-order-traversal-bug.ll | 20 +++++++-------- .../StructurizeCFG/structurizecfg-debug-loc.ll | 22 ++++++++-------- llvm/test/Transforms/StructurizeCFG/switch.ll | 6 ++--- 14 files changed, 97 insertions(+), 97 deletions(-) diff --git a/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug-xfail.ll b/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug-xfail.ll index e9c5415..850696a 100644 --- a/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug-xfail.ll +++ b/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug-xfail.ll @@ -4,21 +4,21 @@ ; FIXME: Merge into backedge-id-bug ; Variant which has an issue with region construction -define amdgpu_kernel void @loop_backedge_misidentified_alt(i32 addrspace(1)* %arg0) #0 { +define amdgpu_kernel void @loop_backedge_misidentified_alt(ptr addrspace(1) %arg0) #0 { entry: - %tmp = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16 - %load1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef + %tmp = load volatile <2 x i32>, ptr addrspace(1) undef, align 16 + %load1 = load volatile <2 x float>, ptr addrspace(1) undef %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i32 %tid - %i.initial = load volatile i32, i32 addrspace(1)* %gep, align 4 + %gep = getelementptr inbounds i32, ptr addrspace(1) %arg0, i32 %tid + %i.initial = load volatile i32, ptr addrspace(1) %gep, align 4 br label %LOOP.HEADER LOOP.HEADER: %i = phi i32 [ %i.final, %END_ELSE_BLOCK ], [ %i.initial, %entry ] call void asm sideeffect "s_nop 0x100b ; loop $0 ", "r,~{memory}"(i32 %i) #0 %tmp12 = zext i32 %i to i64 - %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 %tmp12 - %tmp14 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp13, align 16 + %tmp13 = getelementptr inbounds <4 x i32>, ptr addrspace(1) null, i64 %tmp12 + %tmp14 = load <4 x i32>, ptr addrspace(1) %tmp13, align 16 %tmp15 = extractelement <4 x i32> %tmp14, i64 0 %tmp16 = and i32 %tmp15, 65535 %tmp17 = icmp eq i32 %tmp16, 1 @@ -67,7 +67,7 @@ END_ELSE_BLOCK: RETURN: call void asm sideeffect "s_nop 0x99 ; ClosureEval return", "~{memory}"() #0 - store volatile <2 x float> %load1, <2 x float> addrspace(1)* undef, align 8 + store volatile <2 x float> %load1, ptr addrspace(1) undef, align 8 ret void } diff --git a/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll b/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll index 5b5ea67..6f71ef7 100644 --- a/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll +++ b/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll @@ -14,21 +14,21 @@ ; headers are identified in RPO order, it finds the wrong set of back ; edges. -define amdgpu_kernel void @loop_backedge_misidentified(i32 addrspace(1)* %arg0) #0 { +define amdgpu_kernel void @loop_backedge_misidentified(ptr addrspace(1) %arg0) #0 { ; CHECK-LABEL: @loop_backedge_misidentified( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP:%.*]] = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16 -; CHECK-NEXT: [[LOAD1:%.*]] = load volatile <2 x float>, <2 x float> addrspace(1)* undef +; CHECK-NEXT: [[TMP:%.*]] = load volatile <2 x i32>, ptr addrspace(1) undef, align 16 +; CHECK-NEXT: [[LOAD1:%.*]] = load volatile <2 x float>, ptr addrspace(1) undef ; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() -; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG0:%.*]], i32 [[TID]] -; CHECK-NEXT: [[I_INITIAL:%.*]] = load volatile i32, i32 addrspace(1)* [[GEP]], align 4 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG0:%.*]], i32 [[TID]] +; CHECK-NEXT: [[I_INITIAL:%.*]] = load volatile i32, ptr addrspace(1) [[GEP]], align 4 ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] ; CHECK: LOOP.HEADER: ; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INITIAL]], [[ENTRY:%.*]] ], [ [[TMP10:%.*]], [[FLOW4:%.*]] ] ; CHECK-NEXT: call void asm sideeffect "s_nop 0x100b ; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[I]] to i64 -; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, <4 x i32> addrspace(1)* [[TMP13]], align 16 +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) null, i64 [[TMP12]] +; CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, ptr addrspace(1) [[TMP13]], align 16 ; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP14]], i64 0 ; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 65535 ; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[TMP16]], 1 @@ -88,23 +88,23 @@ define amdgpu_kernel void @loop_backedge_misidentified(i32 addrspace(1)* %arg0) ; CHECK-NEXT: br i1 [[TMP11]], label [[RETURN:%.*]], label [[LOOP_HEADER]] ; CHECK: RETURN: ; CHECK-NEXT: call void asm sideeffect "s_nop 0x99 -; CHECK-NEXT: store volatile <2 x float> [[LOAD1]], <2 x float> addrspace(1)* undef, align 8 +; CHECK-NEXT: store volatile <2 x float> [[LOAD1]], ptr addrspace(1) undef, align 8 ; CHECK-NEXT: ret void ; entry: - %tmp = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16 - %load1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef + %tmp = load volatile <2 x i32>, ptr addrspace(1) undef, align 16 + %load1 = load volatile <2 x float>, ptr addrspace(1) undef %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i32 %tid - %i.initial = load volatile i32, i32 addrspace(1)* %gep, align 4 + %gep = getelementptr inbounds i32, ptr addrspace(1) %arg0, i32 %tid + %i.initial = load volatile i32, ptr addrspace(1) %gep, align 4 br label %LOOP.HEADER LOOP.HEADER: %i = phi i32 [ %i.final, %END_ELSE_BLOCK ], [ %i.initial, %entry ] call void asm sideeffect "s_nop 0x100b ; loop $0 ", "r,~{memory}"(i32 %i) #0 %tmp12 = zext i32 %i to i64 - %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 %tmp12 - %tmp14 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp13, align 16 + %tmp13 = getelementptr inbounds <4 x i32>, ptr addrspace(1) null, i64 %tmp12 + %tmp14 = load <4 x i32>, ptr addrspace(1) %tmp13, align 16 %tmp15 = extractelement <4 x i32> %tmp14, i64 0 %tmp16 = and i32 %tmp15, 65535 %tmp17 = icmp eq i32 %tmp16, 1 @@ -150,7 +150,7 @@ END_ELSE_BLOCK: RETURN: call void asm sideeffect "s_nop 0x99 ; ClosureEval return", "~{memory}"() #0 - store volatile <2 x float> %load1, <2 x float> addrspace(1)* undef, align 8 + store volatile <2 x float> %load1, ptr addrspace(1) undef, align 8 ret void } diff --git a/llvm/test/Transforms/StructurizeCFG/AMDGPU/loop-subregion-misordered.ll b/llvm/test/Transforms/StructurizeCFG/AMDGPU/loop-subregion-misordered.ll index 37fefed..10a3e65 100644 --- a/llvm/test/Transforms/StructurizeCFG/AMDGPU/loop-subregion-misordered.ll +++ b/llvm/test/Transforms/StructurizeCFG/AMDGPU/loop-subregion-misordered.ll @@ -18,21 +18,21 @@ ; ; In this work, we treat the SubRegion as a special case and use its exit block to determine ; the loop and its depth to guard the sorting. -define amdgpu_kernel void @loop_subregion_misordered(i32 addrspace(1)* %arg0) #0 { +define amdgpu_kernel void @loop_subregion_misordered(ptr addrspace(1) %arg0) #0 { ; CHECK-LABEL: @loop_subregion_misordered( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP:%.*]] = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16 -; CHECK-NEXT: [[LOAD1:%.*]] = load volatile <2 x float>, <2 x float> addrspace(1)* undef, align 8 +; CHECK-NEXT: [[TMP:%.*]] = load volatile <2 x i32>, ptr addrspace(1) undef, align 16 +; CHECK-NEXT: [[LOAD1:%.*]] = load volatile <2 x float>, ptr addrspace(1) undef, align 8 ; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() -; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG0:%.*]], i32 [[TID]] -; CHECK-NEXT: [[I_INITIAL:%.*]] = load volatile i32, i32 addrspace(1)* [[GEP]], align 4 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG0:%.*]], i32 [[TID]] +; CHECK-NEXT: [[I_INITIAL:%.*]] = load volatile i32, ptr addrspace(1) [[GEP]], align 4 ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] ; CHECK: LOOP.HEADER: ; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INITIAL]], [[ENTRY:%.*]] ], [ [[TMP5:%.*]], [[FLOW3:%.*]] ] ; CHECK-NEXT: call void asm sideeffect "s_nop 0x100b ; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[I]] to i64 -; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, <4 x i32> addrspace(1)* [[TMP13]], align 16 +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) null, i64 [[TMP12]] +; CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, ptr addrspace(1) [[TMP13]], align 16 ; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP14]], i64 0 ; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 65535 ; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 1 @@ -90,23 +90,23 @@ define amdgpu_kernel void @loop_subregion_misordered(i32 addrspace(1)* %arg0) #0 ; CHECK-NEXT: br label [[FLOW3]] ; CHECK: RETURN: ; CHECK-NEXT: call void asm sideeffect "s_nop 0x99 -; CHECK-NEXT: store volatile <2 x float> [[LOAD1]], <2 x float> addrspace(1)* undef, align 8 +; CHECK-NEXT: store volatile <2 x float> [[LOAD1]], ptr addrspace(1) undef, align 8 ; CHECK-NEXT: ret void ; entry: - %tmp = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16 - %load1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef + %tmp = load volatile <2 x i32>, ptr addrspace(1) undef, align 16 + %load1 = load volatile <2 x float>, ptr addrspace(1) undef %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i32 %tid - %i.initial = load volatile i32, i32 addrspace(1)* %gep, align 4 + %gep = getelementptr inbounds i32, ptr addrspace(1) %arg0, i32 %tid + %i.initial = load volatile i32, ptr addrspace(1) %gep, align 4 br label %LOOP.HEADER LOOP.HEADER: %i = phi i32 [ %i.final, %END_ELSE_BLOCK ], [ %i.initial, %entry ] call void asm sideeffect "s_nop 0x100b ; loop $0 ", "r,~{memory}"(i32 %i) #0 %tmp12 = zext i32 %i to i64 - %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 %tmp12 - %tmp14 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp13, align 16 + %tmp13 = getelementptr inbounds <4 x i32>, ptr addrspace(1) null, i64 %tmp12 + %tmp14 = load <4 x i32>, ptr addrspace(1) %tmp13, align 16 %tmp15 = extractelement <4 x i32> %tmp14, i64 0 %tmp16 = and i32 %tmp15, 65535 %tmp17 = icmp eq i32 %tmp16, 1 @@ -152,7 +152,7 @@ END_ELSE_BLOCK: RETURN: call void asm sideeffect "s_nop 0x99 ; ClosureEval return", "~{memory}"() #0 - store volatile <2 x float> %load1, <2 x float> addrspace(1)* undef, align 8 + store volatile <2 x float> %load1, ptr addrspace(1) undef, align 8 ret void } diff --git a/llvm/test/Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll b/llvm/test/Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll index e91e73c..ae73eed 100644 --- a/llvm/test/Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll +++ b/llvm/test/Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll @@ -22,7 +22,7 @@ end: ret void } -define amdgpu_cs void @nonuniform(i32 addrspace(4)* %ptr) { +define amdgpu_cs void @nonuniform(ptr addrspace(4) %ptr) { ; CHECK-LABEL: @nonuniform( ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[FOR_BODY:%.*]] @@ -79,7 +79,7 @@ end: ret void } -define amdgpu_cs void @uniform_branch_to_nonuniform_subregions(i32 addrspace(4)* %ptr, i32 inreg %data) { +define amdgpu_cs void @uniform_branch_to_nonuniform_subregions(ptr addrspace(4) %ptr, i32 inreg %data) { ; CHECK-LABEL: @uniform_branch_to_nonuniform_subregions( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[DATA:%.*]], 42 diff --git a/llvm/test/Transforms/StructurizeCFG/branch-on-argument.ll b/llvm/test/Transforms/StructurizeCFG/branch-on-argument.ll index cdd4b70..1107469 100644 --- a/llvm/test/Transforms/StructurizeCFG/branch-on-argument.ll +++ b/llvm/test/Transforms/StructurizeCFG/branch-on-argument.ll @@ -3,14 +3,14 @@ ; CHECK-LABEL: @invert_branch_on_arg_inf_loop( ; CHECK: entry: ; CHECK: %arg.inv = xor i1 %arg, true -define void @invert_branch_on_arg_inf_loop(i32 addrspace(1)* %out, i1 %arg) { +define void @invert_branch_on_arg_inf_loop(ptr addrspace(1) %out, i1 %arg) { entry: br i1 %arg, label %for.end, label %sesestart sesestart: br label %for.body for.body: ; preds = %entry, %for.body - store i32 999, i32 addrspace(1)* %out, align 4 + store i32 999, ptr addrspace(1) %out, align 4 br i1 %arg, label %for.body, label %seseend seseend: ret void @@ -25,18 +25,18 @@ for.end: ; preds = %Flow ; CHECK: %arg.inv = xor i1 %arg, true ; CHECK: Flow: ; CHECK: Flow1: -define void @invert_branch_on_arg_jump_into_loop(i32 addrspace(1)* %out, i32 %n, i1 %arg) { +define void @invert_branch_on_arg_jump_into_loop(ptr addrspace(1) %out, i32 %n, i1 %arg) { entry: br label %for.body for.body: %i = phi i32 [0, %entry], [%i.inc, %end.loop] - %ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %i - store i32 %i, i32 addrspace(1)* %ptr, align 4 + %ptr = getelementptr i32, ptr addrspace(1) %out, i32 %i + store i32 %i, ptr addrspace(1) %ptr, align 4 br i1 %arg, label %mid.loop, label %end.loop mid.loop: - store i32 333, i32 addrspace(1)* %out, align 4 + store i32 333, ptr addrspace(1) %out, align 4 br label %for.end end.loop: diff --git a/llvm/test/Transforms/StructurizeCFG/infinite-loop.ll b/llvm/test/Transforms/StructurizeCFG/infinite-loop.ll index 30ffb56..5a10aa6 100644 --- a/llvm/test/Transforms/StructurizeCFG/infinite-loop.ll +++ b/llvm/test/Transforms/StructurizeCFG/infinite-loop.ll @@ -4,12 +4,12 @@ ; This test hits a limitation in StructurizeCFG: it doesn't handle infinite-loops. ; In this case, the IR remains unchanged. -define void @infinite_loop_false(i32 addrspace(1)* %out, i1 %cond) { +define void @infinite_loop_false(ptr addrspace(1) %out, i1 %cond) { ; CHECK-LABEL: @infinite_loop_false( ; CHECK-NEXT: entry: ; CHECK-NEXT: br i1 [[COND:%.*]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] ; CHECK: for.body: -; CHECK-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 +; CHECK-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-NEXT: br label [[FOR_BODY]] ; CHECK: for.end: ; CHECK-NEXT: ret void @@ -18,24 +18,24 @@ entry: br i1 %cond, label %for.end, label %for.body for.body: - store volatile i32 999, i32 addrspace(1)* %out, align 4 + store volatile i32 999, ptr addrspace(1) %out, align 4 br label %for.body for.end: ret void } -define void @infinite_loop_on_branch(i32 addrspace(1)* %out, i1 %cond) { +define void @infinite_loop_on_branch(ptr addrspace(1) %out, i1 %cond) { ; CHECK-LABEL: @infinite_loop_on_branch( ; CHECK-NEXT: entry: ; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] ; CHECK: if.then: ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: -; CHECK-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 +; CHECK-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4 ; CHECK-NEXT: br label [[FOR_BODY]] ; CHECK: if.else: -; CHECK-NEXT: store volatile i32 111, i32 addrspace(1)* [[OUT]], align 4 +; CHECK-NEXT: store volatile i32 111, ptr addrspace(1) [[OUT]], align 4 ; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK: exit: ; CHECK-NEXT: ret void @@ -47,11 +47,11 @@ if.then: br label %for.body for.body: - store volatile i32 999, i32 addrspace(1)* %out, align 4 + store volatile i32 999, ptr addrspace(1) %out, align 4 br label %for.body if.else: - store volatile i32 111, i32 addrspace(1)* %out, align 4 + store volatile i32 111, ptr addrspace(1) %out, align 4 br label %exit exit: diff --git a/llvm/test/Transforms/StructurizeCFG/invert-condition.ll b/llvm/test/Transforms/StructurizeCFG/invert-condition.ll index aa85895..5618d61 100644 --- a/llvm/test/Transforms/StructurizeCFG/invert-condition.ll +++ b/llvm/test/Transforms/StructurizeCFG/invert-condition.ll @@ -4,8 +4,8 @@ define void @invert_condition(i1 %arg) { ; CHECK-LABEL: @invert_condition( ; CHECK-NEXT: bb: -; CHECK-NEXT: [[TMP:%.*]] = load volatile float, float addrspace(1)* undef -; CHECK-NEXT: [[TMP1:%.*]] = load volatile float, float addrspace(1)* undef +; CHECK-NEXT: [[TMP:%.*]] = load volatile float, ptr addrspace(1) undef +; CHECK-NEXT: [[TMP1:%.*]] = load volatile float, ptr addrspace(1) undef ; CHECK-NEXT: br label [[BB2:%.*]] ; CHECK: bb2: ; CHECK-NEXT: [[TMP3:%.*]] = fcmp oge float [[TMP]], [[TMP1]] @@ -16,8 +16,8 @@ define void @invert_condition(i1 %arg) { ; CHECK-NEXT: ret void ; bb: - %tmp = load volatile float, float addrspace(1)* undef - %tmp1 = load volatile float, float addrspace(1)* undef + %tmp = load volatile float, ptr addrspace(1) undef + %tmp1 = load volatile float, ptr addrspace(1) undef br label %bb2 bb2: ; preds = %bb2, %bb diff --git a/llvm/test/Transforms/StructurizeCFG/invert-constantexpr.ll b/llvm/test/Transforms/StructurizeCFG/invert-constantexpr.ll index 880cbfe..c77019e 100644 --- a/llvm/test/Transforms/StructurizeCFG/invert-constantexpr.ll +++ b/llvm/test/Transforms/StructurizeCFG/invert-constantexpr.ll @@ -7,15 +7,15 @@ define void @invert_constantexpr_condition(i32 %arg, i32 %arg1) #0 { ; CHECK-LABEL: @invert_constantexpr_condition( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[TMP:%.*]] = icmp ne i32 [[ARG:%.*]], 0 -; CHECK-NEXT: br i1 icmp eq (i32 ptrtoint (i32* @g to i32), i32 0), label [[BB2:%.*]], label [[FLOW:%.*]] +; CHECK-NEXT: br i1 icmp eq (i32 ptrtoint (ptr @g to i32), i32 0), label [[BB2:%.*]], label [[FLOW:%.*]] ; CHECK: bb2: ; CHECK-NEXT: br label [[FLOW]] ; CHECK: bb3: ; CHECK-NEXT: [[TMP4:%.*]] = phi i1 [ undef, [[FLOW]] ], [ [[TMP7:%.*]], [[BB6:%.*]] ] -; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP4]], icmp eq (i32 ptrtoint (i32* @g to i32), i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP4]], icmp eq (i32 ptrtoint (ptr @g to i32), i32 0) ; CHECK-NEXT: br label [[BB8:%.*]] ; CHECK: Flow: -; CHECK-NEXT: [[TMP0:%.*]] = phi i1 [ [[TMP]], [[BB2]] ], [ icmp ne (i32 ptrtoint (i32* @g to i32), i32 0), [[BB:%.*]] ] +; CHECK-NEXT: [[TMP0:%.*]] = phi i1 [ [[TMP]], [[BB2]] ], [ icmp ne (i32 ptrtoint (ptr @g to i32), i32 0), [[BB:%.*]] ] ; CHECK-NEXT: br i1 [[TMP0]], label [[BB6]], label [[BB3:%.*]] ; CHECK: bb6: ; CHECK-NEXT: [[TMP7]] = icmp slt i32 [[ARG]], [[ARG1:%.*]] @@ -25,14 +25,14 @@ define void @invert_constantexpr_condition(i32 %arg, i32 %arg1) #0 { ; bb: %tmp = icmp eq i32 %arg, 0 - br i1 icmp eq (i32 ptrtoint (i32* @g to i32), i32 0), label %bb2, label %bb6 + br i1 icmp eq (i32 ptrtoint (ptr @g to i32), i32 0), label %bb2, label %bb6 bb2: br i1 %tmp, label %bb3, label %bb6 bb3: %tmp4 = phi i1 [ %tmp7, %bb6 ], [ undef, %bb2 ] - %tmp5 = or i1 %tmp4, icmp eq (i32 ptrtoint (i32* @g to i32), i32 0) + %tmp5 = or i1 %tmp4, icmp eq (i32 ptrtoint (ptr @g to i32), i32 0) br i1 %tmp5, label %bb8, label %bb8 bb6: diff --git a/llvm/test/Transforms/StructurizeCFG/loop-multiple-exits.ll b/llvm/test/Transforms/StructurizeCFG/loop-multiple-exits.ll index 320a8e2..af03be7 100644 --- a/llvm/test/Transforms/StructurizeCFG/loop-multiple-exits.ll +++ b/llvm/test/Transforms/StructurizeCFG/loop-multiple-exits.ll @@ -12,7 +12,7 @@ ; } ; } -define void @loop(i32 addrspace(1)* %out, i32 %cond_a, i32 %cond_b) nounwind uwtable { +define void @loop(ptr addrspace(1) %out, i32 %cond_a, i32 %cond_b) nounwind uwtable { entry: br label %for.cond @@ -23,8 +23,8 @@ for.cond: ; preds = %for.inc, %entry ; CHECK: for.body: for.body: ; preds = %for.cond - %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %i.0 - store i32 %i.0, i32 addrspace(1)* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %out, i32 %i.0 + store i32 %i.0, ptr addrspace(1) %arrayidx, align 4 %cmp1 = icmp ugt i32 %i.0, %cond_b ; CHECK: br i1 %{{[0-9a-zA-Z_.]+}}, label %for.inc, label %[[FLOW1:[0-9a-zA-Z_]+]] br i1 %cmp1, label %for.end, label %for.inc @@ -37,8 +37,8 @@ for.body: ; preds = %for.cond for.inc: ; preds = %for.body %0 = add i32 %cond_a, %i.0 - %arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %0 - store i32 %i.0, i32 addrspace(1)* %arrayidx3, align 4 + %arrayidx3 = getelementptr inbounds i32, ptr addrspace(1) %out, i32 %0 + store i32 %i.0, ptr addrspace(1) %arrayidx3, align 4 %inc = add i32 %i.0, 1 br label %for.cond diff --git a/llvm/test/Transforms/StructurizeCFG/nested-loop-order.ll b/llvm/test/Transforms/StructurizeCFG/nested-loop-order.ll index c226f19..91e9511 100644 --- a/llvm/test/Transforms/StructurizeCFG/nested-loop-order.ll +++ b/llvm/test/Transforms/StructurizeCFG/nested-loop-order.ll @@ -1,7 +1,7 @@ ; RUN: opt -S -structurizecfg %s -o - | FileCheck %s ; RUN: opt -S -passes=structurizecfg %s -o - | FileCheck %s -define void @main(float addrspace(1)* %out) { +define void @main(ptr addrspace(1) %out) { ; CHECK: main_body: ; CHECK: br label %LOOP.outer @@ -32,7 +32,7 @@ ENDLOOP: ; preds = %ENDIF28, %IF29, %LO %temp8.1 = phi float [ %temp8.0.ph, %LOOP ], [ %temp8.0.ph, %IF29 ], [ %tmp35, %ENDIF28 ] %tmp23 = icmp eq i32 %tmp20, 3 %.45 = select i1 %tmp23, float 0.000000e+00, float 1.000000e+00 - store float %.45, float addrspace(1)* %out + store float %.45, ptr addrspace(1) %out ret void ; CHECK: ENDIF: diff --git a/llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll b/llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll index 76caf00..6f1c9a8 100644 --- a/llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll +++ b/llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll @@ -3,7 +3,7 @@ ; CHECK-NOT: br i1 true -define void @blam(i32 addrspace(1)* nocapture %arg, float %arg1, float %arg2) { +define void @blam(ptr addrspace(1) nocapture %arg, float %arg1, float %arg2) { ; CHECK-LABEL: @blam( ; CHECK-NEXT: bb: ; CHECK-NEXT: br label [[BB3:%.*]] @@ -29,7 +29,7 @@ define void @blam(i32 addrspace(1)* nocapture %arg, float %arg1, float %arg2) { ; CHECK-NEXT: [[TMP4:%.*]] = phi i1 [ [[TMP9]], [[BB7]] ], [ true, [[FLOW]] ] ; CHECK-NEXT: br i1 [[TMP4]], label [[BB10:%.*]], label [[BB3]] ; CHECK: bb10: -; CHECK-NEXT: store i32 [[TMP3]], i32 addrspace(1)* [[ARG:%.*]], align 4 +; CHECK-NEXT: store i32 [[TMP3]], ptr addrspace(1) [[ARG:%.*]], align 4 ; CHECK-NEXT: ret void ; bb: @@ -53,6 +53,6 @@ bb7: ; preds = %bb5, %bb3 bb10: ; preds = %bb7, %bb5 %tmp11 = phi i32 [ 15, %bb5 ], [ 255, %bb7 ] - store i32 %tmp11, i32 addrspace(1)* %arg, align 4 + store i32 %tmp11, ptr addrspace(1) %arg, align 4 ret void } diff --git a/llvm/test/Transforms/StructurizeCFG/post-order-traversal-bug.ll b/llvm/test/Transforms/StructurizeCFG/post-order-traversal-bug.ll index 12b18f0..6d6ce86 100644 --- a/llvm/test/Transforms/StructurizeCFG/post-order-traversal-bug.ll +++ b/llvm/test/Transforms/StructurizeCFG/post-order-traversal-bug.ll @@ -7,7 +7,7 @@ ; algorithm requires. ; Function Attrs: nounwind -define void @test(float* nocapture %out, i32 %K1, float* nocapture readonly %nr) { +define void @test(ptr nocapture %out, i32 %K1, ptr nocapture readonly %nr) { ; CHECK: entry: ; CHECK: br label %for.body @@ -28,11 +28,11 @@ for.body: ; preds = %for.body.backedge, ; CHECK: lor.lhs.false: ; CHECK: br label %Flow lor.lhs.false: ; preds = %for.body - %arrayidx = getelementptr inbounds float, float* %nr, i64 %indvars.iv - %tmp1 = load float, float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, ptr %nr, i64 %indvars.iv + %tmp1 = load float, ptr %arrayidx, align 4 %tmp2 = add nsw i64 %indvars.iv, -1 - %arrayidx2 = getelementptr inbounds float, float* %nr, i64 %tmp2 - %tmp3 = load float, float* %arrayidx2, align 4 + %arrayidx2 = getelementptr inbounds float, ptr %nr, i64 %tmp2 + %tmp3 = load float, ptr %arrayidx2, align 4 %cmp3 = fcmp une float %tmp1, %tmp3 br i1 %cmp3, label %if.then, label %for.body.1 @@ -44,15 +44,15 @@ lor.lhs.false: ; preds = %for.body if.then: ; preds = %lor.lhs.false, %for.body %sub4 = sub nsw i32 %tmp0, %prev_start.026 %tmp4 = add nsw i64 %indvars.iv, -1 - %arrayidx8 = getelementptr inbounds float, float* %nr, i64 %tmp4 - %tmp5 = load float, float* %arrayidx8, align 4 + %arrayidx8 = getelementptr inbounds float, ptr %nr, i64 %tmp4 + %tmp5 = load float, ptr %arrayidx8, align 4 br i1 %cmp1, label %for.end, label %for.body.1 ; CHECK: for.end: ; CHECK: ret void for.end: ; preds = %for.body.1, %if.then %best_val.0.lcssa = phi float [ %best_val.233, %for.body.1 ], [ %tmp5, %if.then ] - store float %best_val.0.lcssa, float* %out, align 4 + store float %best_val.0.lcssa, ptr %out, align 4 ret void ; CHECK: Flow1 @@ -84,8 +84,8 @@ for.body.6: ; preds = %for.body.1 ; CHECK: if.then6.6 ; CHECK: br label %for.body.backedge if.then6.6: ; preds = %for.body.6 - %arrayidx8.6 = getelementptr inbounds float, float* %nr, i64 %indvars.iv.next.454 - %tmp29 = load float, float* %arrayidx8.6, align 4 + %arrayidx8.6 = getelementptr inbounds float, ptr %nr, i64 %indvars.iv.next.454 + %tmp29 = load float, ptr %arrayidx8.6, align 4 br label %for.body.backedge ; CHECK: Flow3: diff --git a/llvm/test/Transforms/StructurizeCFG/structurizecfg-debug-loc.ll b/llvm/test/Transforms/StructurizeCFG/structurizecfg-debug-loc.ll index e57464a..d5ee769 100644 --- a/llvm/test/Transforms/StructurizeCFG/structurizecfg-debug-loc.ll +++ b/llvm/test/Transforms/StructurizeCFG/structurizecfg-debug-loc.ll @@ -1,6 +1,6 @@ ; RUN: opt -S -o - -structurizecfg %s | FileCheck %s -define void @if_then_else(i32 addrspace(1)* %out, i1 %arg) !dbg !7 { +define void @if_then_else(ptr addrspace(1) %out, i1 %arg) !dbg !7 { ; CHECK: @if_then_else( ; CHECK: entry: ; CHECK: br i1 {{.*}}, label %if.else, label %Flow, !dbg [[ITE_ENTRY_DL:![0-9]+]] @@ -16,18 +16,18 @@ entry: br i1 %arg, label %if.then, label %if.else, !dbg !8 if.then: - store i32 0, i32 addrspace(1)* %out, !dbg !9 + store i32 0, ptr addrspace(1) %out, !dbg !9 br label %exit, !dbg !10 if.else: - store i32 1, i32 addrspace(1)* %out, !dbg !11 + store i32 1, ptr addrspace(1) %out, !dbg !11 br label %exit, !dbg !12 exit: ret void, !dbg !13 } -define void @while_loop(i32 addrspace(1)* %out) !dbg !14 { +define void @while_loop(ptr addrspace(1) %out) !dbg !14 { ; CHECK: @while_loop( ; CHECK: entry: ; CHECK: br label %while.header, !dbg [[WHILE_ENTRY_DL:![0-9]+]] @@ -47,14 +47,14 @@ while.header: br i1 %cond, label %while.body, label %exit, !dbg !17 while.body: - store i32 1, i32 addrspace(1)* %out, !dbg !18 + store i32 1, ptr addrspace(1) %out, !dbg !18 br label %while.header, !dbg !19 exit: ret void, !dbg !20 } -define void @while_multiple_exits(i32 addrspace(1)* %out) !dbg !21 { +define void @while_multiple_exits(ptr addrspace(1) %out) !dbg !21 { ; CHECK: @while_multiple_exits( ; CHECK: entry: ; CHECK: br label %while.header, !dbg [[WHILEME_ENTRY_DL:![0-9]+]] @@ -81,7 +81,7 @@ exit: ret void, !dbg !27 } -define void @nested_if_then_else(i32 addrspace(1)* %out, i1 %a, i1 %b) !dbg !28 { +define void @nested_if_then_else(ptr addrspace(1) %out, i1 %a, i1 %b) !dbg !28 { ; CHECK: @nested_if_then_else( ; CHECK: entry: ; CHECK: br i1 {{.*}}, label %if.else, label %Flow4, !dbg [[NESTED_ENTRY_DL:![0-9]+]] @@ -116,22 +116,22 @@ if.then: br i1 %b, label %if.then.then, label %if.then.else, !dbg !30 if.then.then: - store i32 0, i32 addrspace(1)* %out, !dbg !31 + store i32 0, ptr addrspace(1) %out, !dbg !31 br label %exit, !dbg !32 if.then.else: - store i32 1, i32 addrspace(1)* %out, !dbg !33 + store i32 1, ptr addrspace(1) %out, !dbg !33 br label %exit, !dbg !34 if.else: br i1 %b, label %if.else.then, label %if.else.else, !dbg !35 if.else.then: - store i32 2, i32 addrspace(1)* %out, !dbg !36 + store i32 2, ptr addrspace(1) %out, !dbg !36 br label %exit, !dbg !37 if.else.else: - store i32 3, i32 addrspace(1)* %out, !dbg !38 + store i32 3, ptr addrspace(1) %out, !dbg !38 br label %exit, !dbg !39 exit: diff --git a/llvm/test/Transforms/StructurizeCFG/switch.ll b/llvm/test/Transforms/StructurizeCFG/switch.ll index 316df57..445c0ab 100644 --- a/llvm/test/Transforms/StructurizeCFG/switch.ll +++ b/llvm/test/Transforms/StructurizeCFG/switch.ll @@ -4,15 +4,15 @@ ; make sure the lower switch pass is always run before structurizecfg. ; CHECK-LABEL: @switch -define void @switch(i32 addrspace(1)* %out, i32 %cond) nounwind { +define void @switch(ptr addrspace(1) %out, i32 %cond) nounwind { entry: ; CHECK: icmp switch i32 %cond, label %done [ i32 0, label %zero] ; CHECK: zero: zero: -; CHECK: store i32 7, i32 addrspace(1)* %out - store i32 7, i32 addrspace(1)* %out +; CHECK: store i32 7, ptr addrspace(1) %out + store i32 7, ptr addrspace(1) %out ; CHECK: br label %done br label %done -- 2.7.4