From bf60a1c546ee496c1dd9336f2a2d8ea989c49558 Mon Sep 17 00:00:00 2001 From: Aakanksha Date: Fri, 25 Feb 2022 17:30:12 +0000 Subject: [PATCH] Avoid comparisons between types of different widths in a loop condition to prevent the loop from behaving unexpectedly This change fixes the code violations flagged in AMD compute CodeQL scan - Query Description: "Comparisons between types of different widths in a loop condition can cause the loop to behave unexpectedly." Differential Revision: https://reviews.llvm.org/D120355 --- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 +- llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp | 2 +- llvm/tools/llvm-pdbutil/StreamUtil.cpp | 2 +- llvm/utils/TableGen/X86RecognizableInstr.cpp | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 9ce83a6..d2622d1 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -357,7 +357,7 @@ SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST) static auto InitializeSubRegFromChannelTableOnce = [this]() { for (auto &Row : SubRegFromChannelTable) Row.fill(AMDGPU::NoSubRegister); - for (uint16_t Idx = 1; Idx < getNumSubRegIndices(); ++Idx) { + for (unsigned Idx = 1; Idx < getNumSubRegIndices(); ++Idx) { unsigned Width = AMDGPUSubRegIdxRanges[Idx].Size / 32; unsigned Offset = AMDGPUSubRegIdxRanges[Idx].Offset / 32; assert(Width < SubRegFromChannelTableWidthMap.size()); diff --git a/llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp b/llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp index ef299ea..0e4f103 100644 --- a/llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp +++ b/llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp @@ -389,7 +389,7 @@ Error DumpOutputStyle::dumpStreamSummary() { uint32_t StreamCount = getPdb().getNumStreams(); uint32_t MaxStreamSize = getPdb().getMaxStreamSize(); - for (uint16_t StreamIdx = 0; StreamIdx < StreamCount; ++StreamIdx) { + for (uint32_t StreamIdx = 0; StreamIdx < StreamCount; ++StreamIdx) { P.formatLine( "Stream {0} ({1} bytes): [{2}]", fmt_align(StreamIdx, AlignStyle::Right, NumDigits(StreamCount)), diff --git a/llvm/tools/llvm-pdbutil/StreamUtil.cpp b/llvm/tools/llvm-pdbutil/StreamUtil.cpp index d0d0a9fb..de906f9 100644 --- a/llvm/tools/llvm-pdbutil/StreamUtil.cpp +++ b/llvm/tools/llvm-pdbutil/StreamUtil.cpp @@ -95,7 +95,7 @@ void llvm::pdb::discoverStreamPurposes(PDBFile &File, } Streams.resize(StreamCount); - for (uint16_t StreamIdx = 0; StreamIdx < StreamCount; ++StreamIdx) { + for (uint32_t StreamIdx = 0; StreamIdx < StreamCount; ++StreamIdx) { if (StreamIdx == OldMSFDirectory) Streams[StreamIdx] = stream(StreamPurpose::Other, "Old MSF Directory", StreamIdx); diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index 4023d8f..ae01014 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -835,7 +835,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC || Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC || Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) { - unsigned Count = Form == X86Local::AddRegFrm ? 8 : 16; + uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16; assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned"); uint8_t currentOpcode; -- 2.7.4