From bf198e2e919ed551794d6eec3fe52e2d1693f0eb Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 29 Apr 2022 09:13:47 -0700 Subject: [PATCH] arm64: dts: imx8mm-venice-gw7902: fix pcie bindings Update the pcie bindings to the correct dt bindings: pcie_phy: - use pcie0_refclk - add required clock-names pcie: - remove pcie_phy clock as it comes from phy driver Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 1b03aa1..f0eccc5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -595,7 +595,8 @@ &pcie_phy { fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; - clocks = <&clk IMX8MM_CLK_DUMMY>; + clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; @@ -604,8 +605,8 @@ pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; -- 2.7.4