From bef27175c716252e4d0caec27b61c572dc92cc90 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 24 Jan 2020 21:51:37 -0500 Subject: [PATCH] AMDGPU: Fix not using f16 fsin/fcos I noticed this because this accidentally started working for GlobalISel. --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 +- .../CodeGen/AMDGPU/fcanonicalize-elimination.ll | 10 ++--- llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll | 48 +++++++++------------- llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll | 48 +++++++++------------- 4 files changed, 44 insertions(+), 66 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index cb03b90..7541c75 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -499,8 +499,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, // F16 - VOP1 Actions. setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); - setOperationAction(ISD::FCOS, MVT::f16, Promote); - setOperationAction(ISD::FSIN, MVT::f16, Promote); + setOperationAction(ISD::FCOS, MVT::f16, Custom); + setOperationAction(ISD::FSIN, MVT::f16, Custom); setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom); setOperationAction(ISD::UINT_TO_FP, MVT::i16, Custom); diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll index cee091a..f567caa 100644 --- a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll +++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll @@ -410,11 +410,10 @@ define amdgpu_kernel void @test_fold_canonicalize_cos_value_f32(float addrspace( } ; GCN-LABEL: test_fold_canonicalize_sin_value_f16: -; GCN: v_sin_f32_e32 [[V0:v[0-9]+]], v{{[0-9]+}} -; GCN: v_cvt_f16_f32_e32 [[V:v[0-9]+]], [[V0]] +; GCN: v_sin_f16_e32 [[V0:v[0-9]+]], v{{[0-9]+}} ; GCN-NOT: v_mul ; GCN-NOT: v_max -; GCN: {{flat|global}}_store_short v[{{[0-9:]+}}], [[V]] +; GCN: {{flat|global}}_store_short v[{{[0-9:]+}}], [[V0]] define amdgpu_kernel void @test_fold_canonicalize_sin_value_f16(half addrspace(1)* %arg) { %id = tail call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr inbounds half, half addrspace(1)* %arg, i32 %id @@ -426,11 +425,10 @@ define amdgpu_kernel void @test_fold_canonicalize_sin_value_f16(half addrspace(1 } ; GCN-LABEL: test_fold_canonicalize_cos_value_f16: -; GCN: v_cos_f32_e32 [[V0:v[0-9]+]], v{{[0-9]+}} -; GCN: v_cvt_f16_f32_e32 [[V:v[0-9]+]], [[V0]] +; GCN: v_cos_f16_e32 [[V0:v[0-9]+]], v{{[0-9]+}} ; GCN-NOT: v_mul ; GCN-NOT: v_max -; GCN: {{flat|global}}_store_short v[{{[0-9:]+}}], [[V]] +; GCN: {{flat|global}}_store_short v[{{[0-9:]+}}], [[V0]] define amdgpu_kernel void @test_fold_canonicalize_cos_value_f16(half addrspace(1)* %arg) { %id = tail call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr inbounds half, half addrspace(1)* %arg, i32 %id diff --git a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll index ea811fc..27002f6 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll @@ -35,11 +35,9 @@ define amdgpu_kernel void @cos_f16(half addrspace(1)* %r, half addrspace(1)* %a) ; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX8-NEXT: v_mul_f32_e32 v0, 0.15915494, v0 -; GFX8-NEXT: v_fract_f32_e32 v0, v0 -; GFX8-NEXT: v_cos_f32_e32 v0, v0 -; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v0 +; GFX8-NEXT: v_mul_f16_e32 v0, 0.15915494, v0 +; GFX8-NEXT: v_fract_f16_e32 v0, v0 +; GFX8-NEXT: v_cos_f16_e32 v2, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: s_endpgm @@ -53,10 +51,8 @@ define amdgpu_kernel void @cos_f16(half addrspace(1)* %r, half addrspace(1)* %a) ; GFX9-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX9-NEXT: v_mul_f32_e32 v0, 0.15915494, v0 -; GFX9-NEXT: v_cos_f32_e32 v0, v0 -; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v0 +; GFX9-NEXT: v_mul_f16_e32 v0, 0.15915494, v0 +; GFX9-NEXT: v_cos_f16_e32 v2, v0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: global_store_short v[0:1], v2, off ; GFX9-NEXT: s_endpgm @@ -105,17 +101,14 @@ define amdgpu_kernel void @cos_v2f16(<2 x half> addrspace(1)* %r, <2 x half> add ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: flat_load_dword v0, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, 0x3118 ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX8-NEXT: v_mul_f32_e32 v1, 0.15915494, v1 -; GFX8-NEXT: v_mul_f32_e32 v0, 0.15915494, v0 -; GFX8-NEXT: v_fract_f32_e32 v1, v1 -; GFX8-NEXT: v_fract_f32_e32 v0, v0 -; GFX8-NEXT: v_cos_f32_e32 v1, v1 -; GFX8-NEXT: v_cos_f32_e32 v0, v0 -; GFX8-NEXT: v_cvt_f16_f32_sdwa v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD -; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v0 +; GFX8-NEXT: v_mul_f16_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_mul_f16_e32 v0, 0.15915494, v0 +; GFX8-NEXT: v_fract_f16_e32 v1, v1 +; GFX8-NEXT: v_fract_f16_e32 v0, v0 +; GFX8-NEXT: v_cos_f16_sdwa v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD +; GFX8-NEXT: v_cos_f16_e32 v3, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_or_b32_e32 v2, v3, v2 @@ -125,23 +118,20 @@ define amdgpu_kernel void @cos_v2f16(<2 x half> addrspace(1)* %r, <2 x half> add ; GFX9-LABEL: cos_v2f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x3118 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v0 -; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-NEXT: v_mul_f32_e32 v1, 0.15915494, v1 -; GFX9-NEXT: v_mul_f32_e32 v0, 0.15915494, v0 -; GFX9-NEXT: v_cos_f32_e32 v1, v1 -; GFX9-NEXT: v_cos_f32_e32 v0, v0 -; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v1 -; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v0 +; GFX9-NEXT: v_mul_f16_e32 v1, 0.15915494, v0 +; GFX9-NEXT: v_cos_f16_e32 v3, v1 +; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-NEXT: v_cos_f16_e32 v2, v0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3 ; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2 +; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3 ; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: s_endpgm %a.val = load <2 x half>, <2 x half> addrspace(1)* %a diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll index 22121c9..bd08e37 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll @@ -35,11 +35,9 @@ define amdgpu_kernel void @sin_f16(half addrspace(1)* %r, half addrspace(1)* %a) ; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX8-NEXT: v_mul_f32_e32 v0, 0.15915494, v0 -; GFX8-NEXT: v_fract_f32_e32 v0, v0 -; GFX8-NEXT: v_sin_f32_e32 v0, v0 -; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v0 +; GFX8-NEXT: v_mul_f16_e32 v0, 0.15915494, v0 +; GFX8-NEXT: v_fract_f16_e32 v0, v0 +; GFX8-NEXT: v_sin_f16_e32 v2, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: s_endpgm @@ -53,10 +51,8 @@ define amdgpu_kernel void @sin_f16(half addrspace(1)* %r, half addrspace(1)* %a) ; GFX9-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX9-NEXT: v_mul_f32_e32 v0, 0.15915494, v0 -; GFX9-NEXT: v_sin_f32_e32 v0, v0 -; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v0 +; GFX9-NEXT: v_mul_f16_e32 v0, 0.15915494, v0 +; GFX9-NEXT: v_sin_f16_e32 v2, v0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: global_store_short v[0:1], v2, off ; GFX9-NEXT: s_endpgm @@ -105,17 +101,14 @@ define amdgpu_kernel void @sin_v2f16(<2 x half> addrspace(1)* %r, <2 x half> add ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: flat_load_dword v0, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, 0x3118 ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX8-NEXT: v_mul_f32_e32 v1, 0.15915494, v1 -; GFX8-NEXT: v_mul_f32_e32 v0, 0.15915494, v0 -; GFX8-NEXT: v_fract_f32_e32 v1, v1 -; GFX8-NEXT: v_fract_f32_e32 v0, v0 -; GFX8-NEXT: v_sin_f32_e32 v1, v1 -; GFX8-NEXT: v_sin_f32_e32 v0, v0 -; GFX8-NEXT: v_cvt_f16_f32_sdwa v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD -; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v0 +; GFX8-NEXT: v_mul_f16_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_mul_f16_e32 v0, 0.15915494, v0 +; GFX8-NEXT: v_fract_f16_e32 v1, v1 +; GFX8-NEXT: v_fract_f16_e32 v0, v0 +; GFX8-NEXT: v_sin_f16_sdwa v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD +; GFX8-NEXT: v_sin_f16_e32 v3, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_or_b32_e32 v2, v3, v2 @@ -125,23 +118,20 @@ define amdgpu_kernel void @sin_v2f16(<2 x half> addrspace(1)* %r, <2 x half> add ; GFX9-LABEL: sin_v2f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x3118 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v0 -; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-NEXT: v_mul_f32_e32 v1, 0.15915494, v1 -; GFX9-NEXT: v_mul_f32_e32 v0, 0.15915494, v0 -; GFX9-NEXT: v_sin_f32_e32 v1, v1 -; GFX9-NEXT: v_sin_f32_e32 v0, v0 -; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v1 -; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v0 +; GFX9-NEXT: v_mul_f16_e32 v1, 0.15915494, v0 +; GFX9-NEXT: v_sin_f16_e32 v3, v1 +; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-NEXT: v_sin_f16_e32 v2, v0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3 ; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2 +; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3 ; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: s_endpgm %a.val = load <2 x half>, <2 x half> addrspace(1)* %a -- 2.7.4