From bed214cf0f7266e5344c1c6e9be5d827aa99ee53 Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Sat, 17 Sep 2022 16:23:32 +0000 Subject: [PATCH] [AArch64][SME] Add intrinsics for enabling/disabling ZA. This adds the intrinsics: * void @llvm.aarch64.sme.za.enable() -> smstart za * void @llvm.aarch64.sme.za.disable() -> smstop za Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D133894 --- llvm/include/llvm/IR/IntrinsicsAArch64.td | 6 ++++++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 16 ++++++++++++++++ llvm/test/CodeGen/AArch64/sme-toggle-pstateza.ll | 16 ++++++++++++++++ 3 files changed, 38 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/sme-toggle-pstateza.ll diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index fc66bdf..8d17ffe 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -2700,6 +2700,12 @@ let TargetPrefix = "aarch64" in { def int_aarch64_sme_set_tpidr2 : DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrNoMem, IntrHasSideEffects]>; + + def int_aarch64_sme_za_enable + : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; + def int_aarch64_sme_za_disable + : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; + // Clamp // diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index f15697d..b482c29 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1157,6 +1157,9 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, } } + if (Subtarget->hasSME()) + setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); + if (Subtarget->hasSVE()) { for (auto VT : {MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64}) { setOperationAction(ISD::BITREVERSE, VT, Custom); @@ -4565,6 +4568,18 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SDValue PStateSM = getPStateSM(DAG, Chain, Attrs, DL, Op.getValueType()); return DAG.getMergeValues({PStateSM, Chain}, DL); } + case Intrinsic::aarch64_sme_za_enable: + return DAG.getNode( + AArch64ISD::SMSTART, DL, MVT::Other, + Op->getOperand(0), // Chain + DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32), + DAG.getConstant(0, DL, MVT::i64), DAG.getConstant(1, DL, MVT::i64)); + case Intrinsic::aarch64_sme_za_disable: + return DAG.getNode( + AArch64ISD::SMSTOP, DL, MVT::Other, + Op->getOperand(0), // Chain + DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32), + DAG.getConstant(0, DL, MVT::i64), DAG.getConstant(1, DL, MVT::i64)); } } @@ -5639,6 +5654,7 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op, return LowerToPredicatedOp(Op, DAG, AArch64ISD::MULHS_PRED); case ISD::MULHU: return LowerToPredicatedOp(Op, DAG, AArch64ISD::MULHU_PRED); + case ISD::INTRINSIC_VOID: case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG); case ISD::INTRINSIC_WO_CHAIN: diff --git a/llvm/test/CodeGen/AArch64/sme-toggle-pstateza.ll b/llvm/test/CodeGen/AArch64/sme-toggle-pstateza.ll new file mode 100644 index 0000000..3c50ab54 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme-toggle-pstateza.ll @@ -0,0 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64 -mattr=+sme -verify-machineinstrs < %s | FileCheck %s + +define void @toggle_pstate_za() { +; CHECK-LABEL: toggle_pstate_za: +; CHECK: // %bb.0: +; CHECK-NEXT: smstart za +; CHECK-NEXT: smstop za +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.za.enable() + call void @llvm.aarch64.sme.za.disable() + ret void +} + +declare void @llvm.aarch64.sme.za.enable() +declare void @llvm.aarch64.sme.za.disable() -- 2.7.4