From beb1857f408b72ef17e3d29a80f53a4bef30eaf3 Mon Sep 17 00:00:00 2001 From: davem Date: Thu, 13 Oct 2011 21:15:44 +0000 Subject: [PATCH] Fix the RTL of some sparc VIS patterns. * config/sparc/sparc.md (UNSPEC_FPMERGE): Delete. (UNSPEC_MUL16AU, UNSPEC_MUL8, UNSPEC_MUL8SU, UNSPEC_MULDSU): New unspecs. (fpmerge_vis): Remove inaccurate comment, represent using vec_select of a vec_concat. (vec_interleave_lowv8qi, vec_interleave_highv8qi): New insns. (fmul8x16_vis, fmul8x16au_vis, fmul8sux16_vis, fmuld8sux16_vis): Reimplement as unspecs and remove inaccurate comments. (vis3_shift_patname): New code attr. (_vis): Rename to "v3". (vis3_addsub_ss_patname): New code attr. (_vis): Rename to "3". * config/sparc/sparc.c (sparc_vis_init_builtins): Update to accommodate pattern name changes. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179943 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 16 ++++++++++ gcc/config/sparc/sparc.c | 32 +++++++++---------- gcc/config/sparc/sparc.md | 79 ++++++++++++++++++++++++++++++++++------------- 3 files changed, 89 insertions(+), 38 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 18c6e88..6a514e8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -64,6 +64,22 @@ 2011-10-12 David S. Miller + * config/sparc/sparc.md (UNSPEC_FPMERGE): Delete. + (UNSPEC_MUL16AU, UNSPEC_MUL8, UNSPEC_MUL8SU, UNSPEC_MULDSU): New + unspecs. + (fpmerge_vis): Remove inaccurate comment, represent using vec_select + of a vec_concat. + (vec_interleave_lowv8qi, vec_interleave_highv8qi): New insns. + (fmul8x16_vis, fmul8x16au_vis, fmul8sux16_vis, fmuld8sux16_vis): + Reimplement as unspecs and remove inaccurate comments. + (vis3_shift_patname): New code attr. + (_vis): Rename to "v3". + (vis3_addsub_ss_patname): New code attr. + (_vis): Rename to + "3". + * config/sparc/sparc.c (sparc_vis_init_builtins): Update to + accommodate pattern name changes. + * config/sparc/sparc.h: Do not force TARGET_VIS3 and TARGET_FMAF to zero when assembler lacks support for such instructions. * config/sparc/sparc.c (sparc_option_override): Clear MASK_VIS3 diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 5ecfe95..fc448cc 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -9496,21 +9496,21 @@ sparc_vis_init_builtins (void) def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis, v4hi_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_fsll16_vis, + def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3, v4hi_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_fslas16_vis, + def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3, v4hi_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_fsrl16_vis, + def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3, v4hi_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_fsra16_vis, + def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3, v4hi_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_fsll32_vis, + def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3, v2si_ftype_v2si_v2si); - def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_fslas32_vis, + def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3, v2si_ftype_v2si_v2si); - def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_fsrl32_vis, + def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3, v2si_ftype_v2si_v2si); - def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_fsra32_vis, + def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3, v2si_ftype_v2si_v2si); if (TARGET_ARCH64) @@ -9527,21 +9527,21 @@ sparc_vis_init_builtins (void) def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis, di_ftype_di_di); - def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_fpadds16_vis, + def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3, v4hi_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_fpadds16s_vis, + def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3, v2hi_ftype_v2hi_v2hi); - def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_fpsubs16_vis, + def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3, v4hi_ftype_v4hi_v4hi); - def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_fpsubs16s_vis, + def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3, v2hi_ftype_v2hi_v2hi); - def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_fpadds32_vis, + def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3, v2si_ftype_v2si_v2si); - def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_fpadds32s_vis, + def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddsi3, v1si_ftype_v1si_v1si); - def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_fpsubs32_vis, + def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3, v2si_ftype_v2si_v2si); - def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_fpsubs32s_vis, + def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubsi3, v1si_ftype_v1si_v1si); if (TARGET_ARCH64) diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 24993fb..c41e259 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -53,7 +53,7 @@ (UNSPEC_FPACK32 41) (UNSPEC_FPACKFIX 42) (UNSPEC_FEXPAND 43) - (UNSPEC_FPMERGE 44) + (UNSPEC_MUL16AU 44) (UNSPEC_MUL16AL 45) (UNSPEC_MUL8UL 46) (UNSPEC_MULDUL 47) @@ -89,6 +89,9 @@ (UNSPEC_FHADD 83) (UNSPEC_FHSUB 84) (UNSPEC_XMUL 85) + (UNSPEC_MUL8 86) + (UNSPEC_MUL8SU 87) + (UNSPEC_MULDSU 88) ]) (define_constants @@ -8004,36 +8007,64 @@ [(set_attr "type" "fga") (set_attr "fptype" "double")]) -;; It may be possible to describe this operation as (1 indexed): -;; (vec_select (vec_duplicate (vec_duplicate (vec_concat 1 2))) -;; 1,5,10,14,19,23,28,32) -;; Note that (vec_merge:V8QI [(V4QI) (V4QI)] (10101010 = 170) doesn't work -;; because vec_merge expects all the operands to be of the same type. (define_insn "fpmerge_vis" [(set (match_operand:V8QI 0 "register_operand" "=e") - (unspec:V8QI [(match_operand:V4QI 1 "register_operand" "f") - (match_operand:V4QI 2 "register_operand" "f")] - UNSPEC_FPMERGE))] + (vec_select:V8QI + (vec_concat:V8QI (match_operand:V4QI 1 "register_operand" "f") + (match_operand:V4QI 2 "register_operand" "f")) + (parallel [(const_int 0) (const_int 4) + (const_int 1) (const_int 5) + (const_int 2) (const_int 6) + (const_int 3) (const_int 7)])))] "TARGET_VIS" "fpmerge\t%1, %2, %0" [(set_attr "type" "fga") (set_attr "fptype" "double")]) +(define_insn "vec_interleave_lowv8qi" + [(set (match_operand:V8QI 0 "register_operand" "=e") + (vec_select:V8QI + (vec_concat:V16QI (match_operand:V8QI 1 "register_operand" "f") + (match_operand:V8QI 2 "register_operand" "f")) + (parallel [(const_int 0) (const_int 8) + (const_int 1) (const_int 9) + (const_int 2) (const_int 10) + (const_int 3) (const_int 11)])))] + "TARGET_VIS" + "fpmerge\t%L1, %L2, %0" + [(set_attr "type" "fga") + (set_attr "fptype" "double")]) + +(define_insn "vec_interleave_highv8qi" + [(set (match_operand:V8QI 0 "register_operand" "=e") + (vec_select:V8QI + (vec_concat:V16QI (match_operand:V8QI 1 "register_operand" "f") + (match_operand:V8QI 2 "register_operand" "f")) + (parallel [(const_int 4) (const_int 12) + (const_int 5) (const_int 13) + (const_int 6) (const_int 14) + (const_int 7) (const_int 15)])))] + "TARGET_VIS" + "fpmerge\t%H1, %H2, %0" + [(set_attr "type" "fga") + (set_attr "fptype" "double")]) + ;; Partitioned multiply instructions (define_insn "fmul8x16_vis" [(set (match_operand:V4HI 0 "register_operand" "=e") - (mult:V4HI (match_operand:V4QI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "e")))] + (unspec:V4HI [(match_operand:V4QI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "e")] + UNSPEC_MUL8))] "TARGET_VIS" "fmul8x16\t%1, %2, %0" [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) -;; Only one of the following two insns can be a multiply. (define_insn "fmul8x16au_vis" [(set (match_operand:V4HI 0 "register_operand" "=e") - (mult:V4HI (match_operand:V4QI 1 "register_operand" "f") - (match_operand:V2HI 2 "register_operand" "f")))] + (unspec:V4HI [(match_operand:V4QI 1 "register_operand" "f") + (match_operand:V2HI 2 "register_operand" "f")] + UNSPEC_MUL16AU))] "TARGET_VIS" "fmul8x16au\t%1, %2, %0" [(set_attr "type" "fpmul") @@ -8049,11 +8080,11 @@ [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) -;; Only one of the following two insns can be a multiply. (define_insn "fmul8sux16_vis" [(set (match_operand:V4HI 0 "register_operand" "=e") - (mult:V4HI (match_operand:V8QI 1 "register_operand" "e") - (match_operand:V4HI 2 "register_operand" "e")))] + (unspec:V4HI [(match_operand:V8QI 1 "register_operand" "e") + (match_operand:V4HI 2 "register_operand" "e")] + UNSPEC_MUL8SU))] "TARGET_VIS" "fmul8sux16\t%1, %2, %0" [(set_attr "type" "fpmul") @@ -8069,11 +8100,11 @@ [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) -;; Only one of the following two insns can be a multiply. (define_insn "fmuld8sux16_vis" [(set (match_operand:V2SI 0 "register_operand" "=e") - (mult:V2SI (match_operand:V4QI 1 "register_operand" "f") - (match_operand:V2HI 2 "register_operand" "f")))] + (unspec:V2SI [(match_operand:V4QI 1 "register_operand" "f") + (match_operand:V2HI 2 "register_operand" "f")] + UNSPEC_MULDSU))] "TARGET_VIS" "fmuld8sux16\t%1, %2, %0" [(set_attr "type" "fpmul") @@ -8440,8 +8471,10 @@ (define_code_iterator vis3_shift [ashift ss_ashift lshiftrt ashiftrt]) (define_code_attr vis3_shift_insn [(ashift "fsll") (ss_ashift "fslas") (lshiftrt "fsrl") (ashiftrt "fsra")]) +(define_code_attr vis3_shift_patname + [(ashift "ashl") (ss_ashift "ssashl") (lshiftrt "lshr") (ashiftrt "ashr")]) -(define_insn "_vis" +(define_insn "v3" [(set (match_operand:V64N8 0 "register_operand" "=") (vis3_shift:V64N8 (match_operand:V64N8 1 "register_operand" "") (match_operand:V64N8 2 "register_operand" "")))] @@ -8490,8 +8523,10 @@ (define_code_iterator vis3_addsub_ss [ss_plus ss_minus]) (define_code_attr vis3_addsub_ss_insn [(ss_plus "fpadds") (ss_minus "fpsubs")]) +(define_code_attr vis3_addsub_ss_patname + [(ss_plus "ssadd") (ss_minus "sssub")]) -(define_insn "_vis" +(define_insn "3" [(set (match_operand:VASS 0 "register_operand" "=") (vis3_addsub_ss:VASS (match_operand:VASS 1 "register_operand" "") (match_operand:VASS 2 "register_operand" "")))] -- 2.7.4