From be3fbe5309145b49622d269dc79b689f631fcdca Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 10 Dec 2008 05:08:50 +0000 Subject: [PATCH] sync.md (sync__12): Replace MIPS_SYNC_OP_12_NOT_NOP with MIPS_SYNC_OP_12_AND. * config/mips/sync.md (sync__12): Replace MIPS_SYNC_OP_12_NOT_NOP with MIPS_SYNC_OP_12_AND. (sync_old__12): Remove third paramater to MIPS_SYNC_OLD_OP_12 macro, replace MIPS_SYNC_OLD_OP_12_NOT_NOP with MIPS_SYNC_OLD_OP_12_AND. (sync_new__12): Replace MIPS_SYNC_NEW_OP_12_NOT_NOP with MIPS_SYNC_NEW_OP_12_AND. (sync_nand_12): Replace MIPS_SYNC_OP_12_NOT_NOT with MIPS_SYNC_OP_12_XOR, reduce length attribute to 40. (sync_old_nand_12): Remove third paramater to MIPS_SYNC_OLD_OP_12 macro, replace MIPS_SYNC_OLD_OP_12_NOT_NOT with MIPS_SYNC_OLD_OP_12_XOR and reduce length attribute to 40. (sync_new_nand_12): Replace MIPS_SYNC_NEW_OP_12_NOT_NOT with MIPS_SYNC_NEW_OP_12_XOR. * config/mips/mips.h (MIPS_SYNC_OP_12, MIPS_SYNC_OP_12_NOT_NOP, MIPS_SYNC_OP_12_NOT_NOT,MIPS_SYNC_OLD_OP_12_NOT_NOP, MIPS_SYNC_OLD_OP_12_NOT_NOT, MIPS_SYNC_NEW_OP_12, MIPS_SYNC_NEW_OP_12_NOT_NOP, MIPS_SYNC_NEW_OP_12_NOT_NOT, MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND, MIPS_SYNC_NEW_NAND): Rewritten to implement new __sync_nand semantics. (MIPS_SYNC_OLD_OP_12): Implement new __sync_nand semantics, and remove third parameter. (MIPS_SYNC_OLD_OP_12_NOT_NOP_REG, MIPS_SYNC_OLD_OP_12_NOT_NOT_REG): Removed. (MIPS_SYNC_OP_12_NOT_NOP): Renamed to MIPS_SYNC_OP_12_AND. (MIPS_SYNC_OP_12_NOT_NOT): Renamed to MIPS_SYNC_OP_12_XOR. (MIPS_SYNC_OLD_OP_12_NOT_NOP): Renamed to MIPS_SYNC_OLD_OP_12_AND. (MIPS_SYNC_OLD_OP_12_NOT_NOT): Renamed to MIPS_SYNC_OLD_OP_12_XOR. (MIPS_SYNC_NEW_OP_12_NOT_NOP): Renamed to MIPS_SYNC_NEW_OP_12_AND. (MIPS_SYNC_NEW_OP_12_NOT_NOT): Renamed to MIPS_SYNC_NEW_OP_12_XOR From-SVN: r142638 --- gcc/ChangeLog | 33 +++++++++++++++++++++ gcc/config/mips/mips.h | 76 ++++++++++++++++++++++++------------------------- gcc/config/mips/sync.md | 18 ++++++------ 3 files changed, 78 insertions(+), 49 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0f59c17..588ce00 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,36 @@ +2008-12-09 David Daney + + * config/mips/sync.md (sync__12): Replace + MIPS_SYNC_OP_12_NOT_NOP with MIPS_SYNC_OP_12_AND. + (sync_old__12): Remove third paramater to + MIPS_SYNC_OLD_OP_12 macro, replace MIPS_SYNC_OLD_OP_12_NOT_NOP + with MIPS_SYNC_OLD_OP_12_AND. + (sync_new__12): Replace MIPS_SYNC_NEW_OP_12_NOT_NOP + with MIPS_SYNC_NEW_OP_12_AND. + (sync_nand_12): Replace MIPS_SYNC_OP_12_NOT_NOT with + MIPS_SYNC_OP_12_XOR, reduce length attribute to 40. + (sync_old_nand_12): Remove third paramater to MIPS_SYNC_OLD_OP_12 + macro, replace MIPS_SYNC_OLD_OP_12_NOT_NOT with + MIPS_SYNC_OLD_OP_12_XOR and reduce length attribute to 40. + (sync_new_nand_12): Replace MIPS_SYNC_NEW_OP_12_NOT_NOT with + MIPS_SYNC_NEW_OP_12_XOR. + * config/mips/mips.h (MIPS_SYNC_OP_12, MIPS_SYNC_OP_12_NOT_NOP, + MIPS_SYNC_OP_12_NOT_NOT,MIPS_SYNC_OLD_OP_12_NOT_NOP, + MIPS_SYNC_OLD_OP_12_NOT_NOT, MIPS_SYNC_NEW_OP_12, + MIPS_SYNC_NEW_OP_12_NOT_NOP, MIPS_SYNC_NEW_OP_12_NOT_NOT, + MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND, MIPS_SYNC_NEW_NAND): Rewritten + to implement new __sync_nand semantics. + (MIPS_SYNC_OLD_OP_12): Implement new __sync_nand semantics, and + remove third parameter. + (MIPS_SYNC_OLD_OP_12_NOT_NOP_REG, + MIPS_SYNC_OLD_OP_12_NOT_NOT_REG): Removed. + (MIPS_SYNC_OP_12_NOT_NOP): Renamed to MIPS_SYNC_OP_12_AND. + (MIPS_SYNC_OP_12_NOT_NOT): Renamed to MIPS_SYNC_OP_12_XOR. + (MIPS_SYNC_OLD_OP_12_NOT_NOP): Renamed to MIPS_SYNC_OLD_OP_12_AND. + (MIPS_SYNC_OLD_OP_12_NOT_NOT): Renamed to MIPS_SYNC_OLD_OP_12_XOR. + (MIPS_SYNC_NEW_OP_12_NOT_NOP): Renamed to MIPS_SYNC_NEW_OP_12_AND. + (MIPS_SYNC_NEW_OP_12_NOT_NOT): Renamed to MIPS_SYNC_NEW_OP_12_XOR + 2008-12-09 Tobias Grosser * graphite.c (graphite_transform_loops): Always call find_transform () diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 6f98cd0..a6444b5 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -3183,24 +3183,25 @@ while (0) - Uses scratch register %4. - NOT_OP are the optional instructions to do a bit-wise not - operation in conjunction with an AND INSN to generate a sync_nand - operation. */ -#define MIPS_SYNC_OP_12(INSN, NOT_OP) \ + AND_OP is an instruction done after INSN to mask INSN's result + with the mask. For most operations, this is an AND with the + inclusive mask (%1). For nand operations -- where the result of + INSN is already correctly masked -- it instead performs a bitwise + not. */ +#define MIPS_SYNC_OP_12(INSN, AND_OP) \ "%(%<%[%|sync\n" \ "1:\tll\t%4,%0\n" \ "\tand\t%@,%4,%2\n" \ - NOT_OP \ "\t" INSN "\t%4,%4,%z3\n" \ - "\tand\t%4,%4,%1\n" \ + AND_OP \ "\tor\t%@,%@,%4\n" \ "\tsc\t%@,%0\n" \ "\tbeq%?\t%@,%.,1b\n" \ "\tnop\n" \ "\tsync%-%]%>%)" -#define MIPS_SYNC_OP_12_NOT_NOP "" -#define MIPS_SYNC_OP_12_NOT_NOT "\tnor\t%4,%4,%.\n" +#define MIPS_SYNC_OP_12_AND "\tand\t%4,%4,%1\n" +#define MIPS_SYNC_OP_12_XOR "\txor\t%4,%4,%1\n" /* Return an asm string that atomically: @@ -3213,29 +3214,25 @@ while (0) - Uses scratch register %5. - NOT_OP are the optional instructions to do a bit-wise not - operation in conjunction with an AND INSN to generate a sync_nand - operation. - - REG is used in conjunction with NOT_OP and is used to select the - register operated on by the INSN. */ -#define MIPS_SYNC_OLD_OP_12(INSN, NOT_OP, REG) \ + AND_OP is an instruction done after INSN to mask INSN's result + with the mask. For most operations, this is an AND with the + inclusive mask (%1). For nand operations -- where the result of + INSN is already correctly masked -- it instead performs a bitwise + not. */ +#define MIPS_SYNC_OLD_OP_12(INSN, AND_OP) \ "%(%<%[%|sync\n" \ "1:\tll\t%0,%1\n" \ "\tand\t%@,%0,%3\n" \ - NOT_OP \ - "\t" INSN "\t%5," REG ",%z4\n" \ - "\tand\t%5,%5,%2\n" \ + "\t" INSN "\t%5,%0,%z4\n" \ + AND_OP \ "\tor\t%@,%@,%5\n" \ "\tsc\t%@,%1\n" \ "\tbeq%?\t%@,%.,1b\n" \ "\tnop\n" \ "\tsync%-%]%>%)" -#define MIPS_SYNC_OLD_OP_12_NOT_NOP "" -#define MIPS_SYNC_OLD_OP_12_NOT_NOP_REG "%0" -#define MIPS_SYNC_OLD_OP_12_NOT_NOT "\tnor\t%5,%0,%.\n" -#define MIPS_SYNC_OLD_OP_12_NOT_NOT_REG "%5" +#define MIPS_SYNC_OLD_OP_12_AND "\tand\t%5,%5,%2\n" +#define MIPS_SYNC_OLD_OP_12_XOR "\txor\t%5,%5,%2\n" /* Return an asm string that atomically: @@ -3246,24 +3243,25 @@ while (0) - Sets %0 to the new value of %1. - NOT_OP are the optional instructions to do a bit-wise not - operation in conjunction with an AND INSN to generate a sync_nand - operation. */ -#define MIPS_SYNC_NEW_OP_12(INSN, NOT_OP) \ + AND_OP is an instruction done after INSN to mask INSN's result + with the mask. For most operations, this is an AND with the + inclusive mask (%1). For nand operations -- where the result of + INSN is already correctly masked -- it instead performs a bitwise + not. */ +#define MIPS_SYNC_NEW_OP_12(INSN, AND_OP) \ "%(%<%[%|sync\n" \ "1:\tll\t%0,%1\n" \ "\tand\t%@,%0,%3\n" \ - NOT_OP \ "\t" INSN "\t%0,%0,%z4\n" \ - "\tand\t%0,%0,%2\n" \ + AND_OP \ "\tor\t%@,%@,%0\n" \ "\tsc\t%@,%1\n" \ "\tbeq%?\t%@,%.,1b\n" \ "\tnop\n" \ "\tsync%-%]%>%)" -#define MIPS_SYNC_NEW_OP_12_NOT_NOP "" -#define MIPS_SYNC_NEW_OP_12_NOT_NOT "\tnor\t%0,%0,%.\n" +#define MIPS_SYNC_NEW_OP_12_AND "\tand\t%0,%0,%2\n" +#define MIPS_SYNC_NEW_OP_12_XOR "\txor\t%0,%0,%2\n" /* Return an asm string that atomically: @@ -3301,7 +3299,7 @@ while (0) /* Return an asm string that atomically: - - Sets memory reference %0 to ~%0 AND %1. + - Sets memory reference %0 to ~(%0 AND %1). SUFFIX is the suffix that should be added to "ll" and "sc" instructions. INSN is the and instruction needed to and a register @@ -3309,8 +3307,8 @@ while (0) #define MIPS_SYNC_NAND(SUFFIX, INSN) \ "%(%<%[%|sync\n" \ "1:\tll" SUFFIX "\t%@,%0\n" \ - "\tnor\t%@,%@,%.\n" \ "\t" INSN "\t%@,%@,%1\n" \ + "\tnor\t%@,%@,%.\n" \ "\tsc" SUFFIX "\t%@,%0\n" \ "\tbeq%?\t%@,%.,1b\n" \ "\tnop\n" \ @@ -3318,7 +3316,7 @@ while (0) /* Return an asm string that atomically: - - Sets memory reference %1 to ~%1 AND %2. + - Sets memory reference %1 to ~(%1 AND %2). - Sets register %0 to the old value of memory reference %1. @@ -3328,8 +3326,8 @@ while (0) #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \ "%(%<%[%|sync\n" \ "1:\tll" SUFFIX "\t%0,%1\n" \ - "\tnor\t%@,%0,%.\n" \ - "\t" INSN "\t%@,%@,%2\n" \ + "\t" INSN "\t%@,%0,%2\n" \ + "\tnor\t%@,%@,%.\n" \ "\tsc" SUFFIX "\t%@,%1\n" \ "\tbeq%?\t%@,%.,1b\n" \ "\tnop\n" \ @@ -3337,7 +3335,7 @@ while (0) /* Return an asm string that atomically: - - Sets memory reference %1 to ~%1 AND %2. + - Sets memory reference %1 to ~(%1 AND %2). - Sets register %0 to the new value of memory reference %1. @@ -3347,11 +3345,11 @@ while (0) #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \ "%(%<%[%|sync\n" \ "1:\tll" SUFFIX "\t%0,%1\n" \ - "\tnor\t%0,%0,%.\n" \ - "\t" INSN "\t%@,%0,%2\n" \ + "\t" INSN "\t%0,%0,%2\n" \ + "\tnor\t%@,%0,%.\n" \ "\tsc" SUFFIX "\t%@,%1\n" \ "\tbeq%?\t%@,%.,1b%~\n" \ - "\t" INSN "\t%0,%0,%2\n" \ + "\tnor\t%0,%0,%.\n" \ "\tsync%-%]%>%)" /* Return an asm string that atomically: diff --git a/gcc/config/mips/sync.md b/gcc/config/mips/sync.md index 286ca36..f053be6 100644 --- a/gcc/config/mips/sync.md +++ b/gcc/config/mips/sync.md @@ -127,7 +127,7 @@ "GENERATE_LL_SC" { return (mips_output_sync_loop - (MIPS_SYNC_OP_12 ("", MIPS_SYNC_OP_12_NOT_NOP))); + (MIPS_SYNC_OP_12 ("", MIPS_SYNC_OP_12_AND))); } [(set_attr "length" "40")]) @@ -164,8 +164,7 @@ "GENERATE_LL_SC" { return (mips_output_sync_loop - (MIPS_SYNC_OLD_OP_12 ("", MIPS_SYNC_OLD_OP_12_NOT_NOP, - MIPS_SYNC_OLD_OP_12_NOT_NOP_REG))); + (MIPS_SYNC_OLD_OP_12 ("", MIPS_SYNC_OLD_OP_12_AND))); } [(set_attr "length" "40")]) @@ -207,7 +206,7 @@ "GENERATE_LL_SC" { return (mips_output_sync_loop - (MIPS_SYNC_NEW_OP_12 ("", MIPS_SYNC_NEW_OP_12_NOT_NOP))); + (MIPS_SYNC_NEW_OP_12 ("", MIPS_SYNC_NEW_OP_12_AND))); } [(set_attr "length" "40")]) @@ -239,9 +238,9 @@ "GENERATE_LL_SC" { return (mips_output_sync_loop - (MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_NOT_NOT))); + (MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_XOR))); } - [(set_attr "length" "44")]) + [(set_attr "length" "40")]) (define_expand "sync_old_nand" [(parallel [ @@ -274,10 +273,9 @@ "GENERATE_LL_SC" { return (mips_output_sync_loop - (MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_NOT_NOT, - MIPS_SYNC_OLD_OP_12_NOT_NOT_REG))); + (MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_XOR))); } - [(set_attr "length" "44")]) + [(set_attr "length" "40")]) (define_expand "sync_new_nand" [(parallel [ @@ -315,7 +313,7 @@ "GENERATE_LL_SC" { return (mips_output_sync_loop - (MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_NOT_NOT))); + (MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_XOR))); } [(set_attr "length" "40")]) -- 2.7.4