From be35264ab5a38e8367dde49acfbfa1dd71230dfc Mon Sep 17 00:00:00 2001 From: Sean Silva Date: Tue, 8 Sep 2020 15:49:50 -0700 Subject: [PATCH] Wordsmith RegionBranchOpInterface verification errors I was having a lot of trouble parsing the messages. In particular, the messages like: ``` :3:8: error: 'scf.if' op along control flow edge from Region #0 to scf.if source #1 type '!npcomprt.tensor' should match input #1 type 'tensor' ``` In particular, one thing that kept catching me was parsing the "to scf.if source #1 type" as one thing, but really it is "to parent results: source type #1". Differential Revision: https://reviews.llvm.org/D87334 --- mlir/lib/Interfaces/ControlFlowInterfaces.cpp | 15 +++++++-------- mlir/test/Dialect/SCF/invalid.mlir | 4 ++-- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/mlir/lib/Interfaces/ControlFlowInterfaces.cpp b/mlir/lib/Interfaces/ControlFlowInterfaces.cpp index fc79c82..4984862 100644 --- a/mlir/lib/Interfaces/ControlFlowInterfaces.cpp +++ b/mlir/lib/Interfaces/ControlFlowInterfaces.cpp @@ -103,13 +103,13 @@ static LogicalResult verifyTypesAlongAllEdges( if (sourceNo) diag << "Region #" << sourceNo.getValue(); else - diag << op->getName(); + diag << "parent operands"; diag << " to "; if (succRegionNo) diag << "Region #" << succRegionNo.getValue(); else - diag << op->getName(); + diag << "parent results"; return diag; }; @@ -117,10 +117,9 @@ static LogicalResult verifyTypesAlongAllEdges( TypeRange succInputsTypes = succ.getSuccessorInputs().getTypes(); if (sourceTypes.size() != succInputsTypes.size()) { InFlightDiagnostic diag = op->emitOpError(" region control flow edge "); - return printEdgeName(diag) - << " has " << sourceTypes.size() - << " source operands, but target successor needs " - << succInputsTypes.size(); + return printEdgeName(diag) << ": source has " << sourceTypes.size() + << " operands, but target successor needs " + << succInputsTypes.size(); } for (auto typesIdx : @@ -130,8 +129,8 @@ static LogicalResult verifyTypesAlongAllEdges( if (sourceType != inputType) { InFlightDiagnostic diag = op->emitOpError(" along control flow edge "); return printEdgeName(diag) - << " source #" << typesIdx.index() << " type " << sourceType - << " should match input #" << typesIdx.index() << " type " + << ": source type #" << typesIdx.index() << " " << sourceType + << " should match input type #" << typesIdx.index() << " " << inputType; } } diff --git a/mlir/test/Dialect/SCF/invalid.mlir b/mlir/test/Dialect/SCF/invalid.mlir index 517e885..06b902d 100644 --- a/mlir/test/Dialect/SCF/invalid.mlir +++ b/mlir/test/Dialect/SCF/invalid.mlir @@ -325,7 +325,7 @@ func @reduceReturn_not_inside_reduce(%arg0 : f32) { func @std_if_incorrect_yield(%arg0: i1, %arg1: f32) { - // expected-error@+1 {{region control flow edge from Region #0 to scf.if has 1 source operands, but target successor needs 2}} + // expected-error@+1 {{region control flow edge from Region #0 to parent results: source has 1 operands, but target successor needs 2}} %x, %y = scf.if %arg0 -> (f32, f32) { %0 = addf %arg1, %arg1 : f32 scf.yield %0 : f32 @@ -401,7 +401,7 @@ func @std_for_operands_mismatch_3(%arg0 : index, %arg1 : index, %arg2 : index) { func @std_for_operands_mismatch_4(%arg0 : index, %arg1 : index, %arg2 : index) { %s0 = constant 0.0 : f32 %t0 = constant 1.0 : f32 - // expected-error @+1 {{along control flow edge from Region #0 to Region #0 source #1 type 'i32' should match input #1 type 'f32'}} + // expected-error @+1 {{along control flow edge from Region #0 to Region #0: source type #1 'i32' should match input type #1 'f32'}} %result1:2 = scf.for %i0 = %arg0 to %arg1 step %arg2 iter_args(%si = %s0, %ti = %t0) -> (f32, f32) { %sn = addf %si, %si : f32 -- 2.7.4