From be30fddc7c6d0a75cf0777cf24591c3a6439e2c6 Mon Sep 17 00:00:00 2001 From: Krzysztof Czurylo Date: Wed, 30 Jul 2008 10:19:08 -0700 Subject: [PATCH] 965: Fix color clamping issues Patch is correctly applied this time. --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index ad414f4..8759826 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1165,6 +1165,27 @@ void brw_vs_emit(struct brw_vs_compile *c ) brw_MOV(p, get_dst(c, inst->DstReg), dst); } + /* Result color clamping. + * + * When destination register is an output register and + * it's primary/secondary front/back color, we have to clamp + * the result to [0,1]. This is done by enabling the + * saturation bit for the last instruction. + * + * We don't use brw_set_saturate() as it modifies + * p->current->header.saturate, which affects all the subsequent + * instructions. Instead, we directly modify the header + * of the last (already stored) instruction. + */ + if (inst->DstReg.File == PROGRAM_OUTPUT) { + if ((inst->DstReg.Index == VERT_RESULT_COL0) + || (inst->DstReg.Index == VERT_RESULT_COL1) + || (inst->DstReg.Index == VERT_RESULT_BFC0) + || (inst->DstReg.Index == VERT_RESULT_BFC1)) { + p->store[p->nr_insn-1].header.saturate = 1; + } + } + release_tmps(c); } -- 2.7.4