From be161e66d6108e56d40c116a4ee12668d6b8d960 Mon Sep 17 00:00:00 2001 From: Christoph Bumiller Date: Thu, 22 Mar 2012 11:58:31 +0100 Subject: [PATCH] nv50/ir/opt: check BB equality before instruction ordering in CSE --- src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp index 35ddca3..259bb56 100644 --- a/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp +++ b/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp @@ -2096,7 +2096,7 @@ LocalCSE::visit(BasicBlock *bb) for (Value::UseIterator it = src->uses.begin(); it != src->uses.end(); ++it) { Instruction *ik = (*it)->getInsn(); - if (ik && ik->serial < ir->serial && ik->bb == ir->bb) + if (ik && ik->bb == ir->bb && ik->serial < ir->serial) if (tryReplace(&ir, ik)) break; } -- 2.7.4