From be05b85db9fbff9fa047a826d1f19a64be900e33 Mon Sep 17 00:00:00 2001
From: David Green <david.green@arm.com>
Date: Fri, 28 Jun 2019 07:21:11 +0000
Subject: [PATCH] [ARM] Select MVE add and sub

This adds the first few patterns for MVE code generation, adding simple integer
add and sub patterns.

Initial code by David Sherwood

Differential Revision: https://reviews.llvm.org/D63255

llvm-svn: 364627
---
 llvm/lib/Target/ARM/ARMInstrMVE.td           | 18 ++++++++
 llvm/test/CodeGen/Thumb2/mve-simple-arith.ll | 64 ++++++++++++++++++++++++++++
 2 files changed, 82 insertions(+)
 create mode 100644 llvm/test/CodeGen/Thumb2/mve-simple-arith.ll

diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index dc6bf33..6585e5b 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -1839,10 +1839,28 @@ def MVE_VADDi8  : MVE_VADD<"i8",  0b00>;
 def MVE_VADDi16 : MVE_VADD<"i16", 0b01>;
 def MVE_VADDi32 : MVE_VADD<"i32", 0b10>;
 
+let Predicates = [HasMVEInt] in {
+  def : Pat<(v16i8 (add (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
+            (v16i8 (MVE_VADDi8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
+  def : Pat<(v8i16 (add (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
+            (v8i16 (MVE_VADDi16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
+  def : Pat<(v4i32 (add (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
+            (v4i32 (MVE_VADDi32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
+}
+
 def MVE_VSUBi8  : MVE_VSUB<"i8",  0b00>;
 def MVE_VSUBi16 : MVE_VSUB<"i16", 0b01>;
 def MVE_VSUBi32 : MVE_VSUB<"i32", 0b10>;
 
+let Predicates = [HasMVEInt] in {
+  def : Pat<(v16i8 (sub (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
+            (v16i8 (MVE_VSUBi8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
+  def : Pat<(v8i16 (sub (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
+            (v8i16 (MVE_VSUBi16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
+  def : Pat<(v4i32 (sub (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
+            (v4i32 (MVE_VSUBi32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
+}
+
 class MVE_VQADDSUB<string iname, string suffix, bit U, bit subtract,
                    bits<2> size, list<dag> pattern=[]>
   : MVE_int<iname, suffix, size, pattern> {
diff --git a/llvm/test/CodeGen/Thumb2/mve-simple-arith.ll b/llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
new file mode 100644
index 0000000..b2a846b
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
+
+define arm_aapcs_vfpcc <16 x i8> @add_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
+; CHECK-LABEL: add_int8_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vadd.i8 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = add <16 x i8> %src1, %src2
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @add_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
+; CHECK-LABEL: add_int16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vadd.i16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = add <8 x i16> %src1, %src2
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @add_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
+; CHECK-LABEL: add_int32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vadd.i32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = add nsw <4 x i32> %src1, %src2
+  ret <4 x i32> %0
+}
+
+
+define arm_aapcs_vfpcc <16 x i8> @sub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
+; CHECK-LABEL: sub_int8_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vsub.i8 q0, q1, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = sub <16 x i8> %src2, %src1
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @sub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
+; CHECK-LABEL: sub_int16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vsub.i16 q0, q1, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = sub <8 x i16> %src2, %src1
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @sub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
+; CHECK-LABEL: sub_int32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vsub.i32 q0, q1, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = sub nsw <4 x i32> %src2, %src1
+  ret <4 x i32> %0
+}
-- 
2.7.4