From bde90be2cddc06371ee80a258bf6855d0f346324 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Wed, 3 Oct 2018 18:51:11 +0100 Subject: [PATCH] AArch64: Constraint disassembler and assembler changes. This patch wires in the new constraint verifiers into the assembler and disassembler. Because of this the MOVPRFX tests have to be split out from the generic SVE tests into their own tests so warnings can be ignored. These tests are only intended to test the encoding correctness and not the constraints. gas/ * testsuite/gas/aarch64/sve-movprfx.d: New test. * testsuite/gas/aarch64/sve-movprfx.s: New test. * testsuite/gas/aarch64/sve.d: Refactor. * testsuite/gas/aarch64/sve.s: Refactor. * testsuite/gas/aarch64/sysreg-diagnostic.d: Update. opcodes/ * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier. * aarch64-dis.c (print_operands): Refactor to take notes. (print_verifier_notes): New. (print_aarch64_insn): Apply constraint verifier. (print_insn_aarch64_word): Update call to print_aarch64_insn. * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format. --- gas/ChangeLog | 8 ++ gas/testsuite/gas/aarch64/sve-movprfx.d | 130 ++++++++++++++++++++++++++ gas/testsuite/gas/aarch64/sve-movprfx.s | 122 ++++++++++++++++++++++++ gas/testsuite/gas/aarch64/sve.d | 122 ------------------------ gas/testsuite/gas/aarch64/sve.s | 122 ------------------------ gas/testsuite/gas/aarch64/sysreg-diagnostic.d | 2 +- opcodes/ChangeLog | 9 ++ opcodes/aarch64-asm.c | 34 ++++++- opcodes/aarch64-dis.c | 66 +++++++++++-- opcodes/aarch64-opc.c | 6 +- 10 files changed, 365 insertions(+), 256 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sve-movprfx.d create mode 100644 gas/testsuite/gas/aarch64/sve-movprfx.s diff --git a/gas/ChangeLog b/gas/ChangeLog index 56609f4..aa684f7 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,13 @@ 2018-10-03 Tamar Christina + * testsuite/gas/aarch64/sve-movprfx.d: New test. + * testsuite/gas/aarch64/sve-movprfx.s: New test. + * testsuite/gas/aarch64/sve.d: Refactor. + * testsuite/gas/aarch64/sve.s: Refactor. + * testsuite/gas/aarch64/sysreg-diagnostic.d: Update. + +2018-10-03 Tamar Christina + * config/tc-aarch64.c (force_automatic_sequence_close, aarch64_frob_section): New. * config/tc-aarch64.h (tc_frob_section, aarch64_frob_section): New. diff --git a/gas/testsuite/gas/aarch64/sve-movprfx.d b/gas/testsuite/gas/aarch64/sve-movprfx.d new file mode 100644 index 0000000..a589b72 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx.d @@ -0,0 +1,130 @@ +#as: -march=armv8-a+sve -I$srcdir/$subdir -W +#objdump: -dr -M no-notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 0420bc00 movprfx z0, z0 +[^:]+: 0420bc00 movprfx z0, z0 +[^:]+: 0420bc01 movprfx z1, z0 +[^:]+: 0420bc01 movprfx z1, z0 +[^:]+: 0420bc1f movprfx z31, z0 +[^:]+: 0420bc1f movprfx z31, z0 +[^:]+: 0420bc40 movprfx z0, z2 +[^:]+: 0420bc40 movprfx z0, z2 +[^:]+: 0420bfe0 movprfx z0, z31 +[^:]+: 0420bfe0 movprfx z0, z31 +[^:]+: 04102000 movprfx z0.b, p0/z, z0.b +[^:]+: 04102000 movprfx z0.b, p0/z, z0.b +[^:]+: 04102001 movprfx z1.b, p0/z, z0.b +[^:]+: 04102001 movprfx z1.b, p0/z, z0.b +[^:]+: 0410201f movprfx z31.b, p0/z, z0.b +[^:]+: 0410201f movprfx z31.b, p0/z, z0.b +[^:]+: 04102800 movprfx z0.b, p2/z, z0.b +[^:]+: 04102800 movprfx z0.b, p2/z, z0.b +[^:]+: 04103c00 movprfx z0.b, p7/z, z0.b +[^:]+: 04103c00 movprfx z0.b, p7/z, z0.b +[^:]+: 04102060 movprfx z0.b, p0/z, z3.b +[^:]+: 04102060 movprfx z0.b, p0/z, z3.b +[^:]+: 041023e0 movprfx z0.b, p0/z, z31.b +[^:]+: 041023e0 movprfx z0.b, p0/z, z31.b +[^:]+: 04112000 movprfx z0.b, p0/m, z0.b +[^:]+: 04112000 movprfx z0.b, p0/m, z0.b +[^:]+: 04112001 movprfx z1.b, p0/m, z0.b +[^:]+: 04112001 movprfx z1.b, p0/m, z0.b +[^:]+: 0411201f movprfx z31.b, p0/m, z0.b +[^:]+: 0411201f movprfx z31.b, p0/m, z0.b +[^:]+: 04112800 movprfx z0.b, p2/m, z0.b +[^:]+: 04112800 movprfx z0.b, p2/m, z0.b +[^:]+: 04113c00 movprfx z0.b, p7/m, z0.b +[^:]+: 04113c00 movprfx z0.b, p7/m, z0.b +[^:]+: 04112060 movprfx z0.b, p0/m, z3.b +[^:]+: 04112060 movprfx z0.b, p0/m, z3.b +[^:]+: 041123e0 movprfx z0.b, p0/m, z31.b +[^:]+: 041123e0 movprfx z0.b, p0/m, z31.b +[^:]+: 04502000 movprfx z0.h, p0/z, z0.h +[^:]+: 04502000 movprfx z0.h, p0/z, z0.h +[^:]+: 04502001 movprfx z1.h, p0/z, z0.h +[^:]+: 04502001 movprfx z1.h, p0/z, z0.h +[^:]+: 0450201f movprfx z31.h, p0/z, z0.h +[^:]+: 0450201f movprfx z31.h, p0/z, z0.h +[^:]+: 04502800 movprfx z0.h, p2/z, z0.h +[^:]+: 04502800 movprfx z0.h, p2/z, z0.h +[^:]+: 04503c00 movprfx z0.h, p7/z, z0.h +[^:]+: 04503c00 movprfx z0.h, p7/z, z0.h +[^:]+: 04502060 movprfx z0.h, p0/z, z3.h +[^:]+: 04502060 movprfx z0.h, p0/z, z3.h +[^:]+: 045023e0 movprfx z0.h, p0/z, z31.h +[^:]+: 045023e0 movprfx z0.h, p0/z, z31.h +[^:]+: 04512000 movprfx z0.h, p0/m, z0.h +[^:]+: 04512000 movprfx z0.h, p0/m, z0.h +[^:]+: 04512001 movprfx z1.h, p0/m, z0.h +[^:]+: 04512001 movprfx z1.h, p0/m, z0.h +[^:]+: 0451201f movprfx z31.h, p0/m, z0.h +[^:]+: 0451201f movprfx z31.h, p0/m, z0.h +[^:]+: 04512800 movprfx z0.h, p2/m, z0.h +[^:]+: 04512800 movprfx z0.h, p2/m, z0.h +[^:]+: 04513c00 movprfx z0.h, p7/m, z0.h +[^:]+: 04513c00 movprfx z0.h, p7/m, z0.h +[^:]+: 04512060 movprfx z0.h, p0/m, z3.h +[^:]+: 04512060 movprfx z0.h, p0/m, z3.h +[^:]+: 045123e0 movprfx z0.h, p0/m, z31.h +[^:]+: 045123e0 movprfx z0.h, p0/m, z31.h +[^:]+: 04902000 movprfx z0.s, p0/z, z0.s +[^:]+: 04902000 movprfx z0.s, p0/z, z0.s +[^:]+: 04902001 movprfx z1.s, p0/z, z0.s +[^:]+: 04902001 movprfx z1.s, p0/z, z0.s +[^:]+: 0490201f movprfx z31.s, p0/z, z0.s +[^:]+: 0490201f movprfx z31.s, p0/z, z0.s +[^:]+: 04902800 movprfx z0.s, p2/z, z0.s +[^:]+: 04902800 movprfx z0.s, p2/z, z0.s +[^:]+: 04903c00 movprfx z0.s, p7/z, z0.s +[^:]+: 04903c00 movprfx z0.s, p7/z, z0.s +[^:]+: 04902060 movprfx z0.s, p0/z, z3.s +[^:]+: 04902060 movprfx z0.s, p0/z, z3.s +[^:]+: 049023e0 movprfx z0.s, p0/z, z31.s +[^:]+: 049023e0 movprfx z0.s, p0/z, z31.s +[^:]+: 04912000 movprfx z0.s, p0/m, z0.s +[^:]+: 04912000 movprfx z0.s, p0/m, z0.s +[^:]+: 04912001 movprfx z1.s, p0/m, z0.s +[^:]+: 04912001 movprfx z1.s, p0/m, z0.s +[^:]+: 0491201f movprfx z31.s, p0/m, z0.s +[^:]+: 0491201f movprfx z31.s, p0/m, z0.s +[^:]+: 04912800 movprfx z0.s, p2/m, z0.s +[^:]+: 04912800 movprfx z0.s, p2/m, z0.s +[^:]+: 04913c00 movprfx z0.s, p7/m, z0.s +[^:]+: 04913c00 movprfx z0.s, p7/m, z0.s +[^:]+: 04912060 movprfx z0.s, p0/m, z3.s +[^:]+: 04912060 movprfx z0.s, p0/m, z3.s +[^:]+: 049123e0 movprfx z0.s, p0/m, z31.s +[^:]+: 049123e0 movprfx z0.s, p0/m, z31.s +[^:]+: 04d02000 movprfx z0.d, p0/z, z0.d +[^:]+: 04d02000 movprfx z0.d, p0/z, z0.d +[^:]+: 04d02001 movprfx z1.d, p0/z, z0.d +[^:]+: 04d02001 movprfx z1.d, p0/z, z0.d +[^:]+: 04d0201f movprfx z31.d, p0/z, z0.d +[^:]+: 04d0201f movprfx z31.d, p0/z, z0.d +[^:]+: 04d02800 movprfx z0.d, p2/z, z0.d +[^:]+: 04d02800 movprfx z0.d, p2/z, z0.d +[^:]+: 04d03c00 movprfx z0.d, p7/z, z0.d +[^:]+: 04d03c00 movprfx z0.d, p7/z, z0.d +[^:]+: 04d02060 movprfx z0.d, p0/z, z3.d +[^:]+: 04d02060 movprfx z0.d, p0/z, z3.d +[^:]+: 04d023e0 movprfx z0.d, p0/z, z31.d +[^:]+: 04d023e0 movprfx z0.d, p0/z, z31.d +[^:]+: 04d12000 movprfx z0.d, p0/m, z0.d +[^:]+: 04d12000 movprfx z0.d, p0/m, z0.d +[^:]+: 04d12001 movprfx z1.d, p0/m, z0.d +[^:]+: 04d12001 movprfx z1.d, p0/m, z0.d +[^:]+: 04d1201f movprfx z31.d, p0/m, z0.d +[^:]+: 04d1201f movprfx z31.d, p0/m, z0.d +[^:]+: 04d12800 movprfx z0.d, p2/m, z0.d +[^:]+: 04d12800 movprfx z0.d, p2/m, z0.d +[^:]+: 04d13c00 movprfx z0.d, p7/m, z0.d +[^:]+: 04d13c00 movprfx z0.d, p7/m, z0.d +[^:]+: 04d12060 movprfx z0.d, p0/m, z3.d +[^:]+: 04d12060 movprfx z0.d, p0/m, z3.d +[^:]+: 04d123e0 movprfx z0.d, p0/m, z31.d +[^:]+: 04d123e0 movprfx z0.d, p0/m, z31.d diff --git a/gas/testsuite/gas/aarch64/sve-movprfx.s b/gas/testsuite/gas/aarch64/sve-movprfx.s new file mode 100644 index 0000000..35be73c --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx.s @@ -0,0 +1,122 @@ + movprfx z0, z0 + MOVPRFX Z0, Z0 + movprfx z1, z0 + MOVPRFX Z1, Z0 + movprfx z31, z0 + MOVPRFX Z31, Z0 + movprfx z0, z2 + MOVPRFX Z0, Z2 + movprfx z0, z31 + MOVPRFX Z0, Z31 + movprfx z0.b, p0/z, z0.b + MOVPRFX Z0.B, P0/Z, Z0.B + movprfx z1.b, p0/z, z0.b + MOVPRFX Z1.B, P0/Z, Z0.B + movprfx z31.b, p0/z, z0.b + MOVPRFX Z31.B, P0/Z, Z0.B + movprfx z0.b, p2/z, z0.b + MOVPRFX Z0.B, P2/Z, Z0.B + movprfx z0.b, p7/z, z0.b + MOVPRFX Z0.B, P7/Z, Z0.B + movprfx z0.b, p0/z, z3.b + MOVPRFX Z0.B, P0/Z, Z3.B + movprfx z0.b, p0/z, z31.b + MOVPRFX Z0.B, P0/Z, Z31.B + movprfx z0.b, p0/m, z0.b + MOVPRFX Z0.B, P0/M, Z0.B + movprfx z1.b, p0/m, z0.b + MOVPRFX Z1.B, P0/M, Z0.B + movprfx z31.b, p0/m, z0.b + MOVPRFX Z31.B, P0/M, Z0.B + movprfx z0.b, p2/m, z0.b + MOVPRFX Z0.B, P2/M, Z0.B + movprfx z0.b, p7/m, z0.b + MOVPRFX Z0.B, P7/M, Z0.B + movprfx z0.b, p0/m, z3.b + MOVPRFX Z0.B, P0/M, Z3.B + movprfx z0.b, p0/m, z31.b + MOVPRFX Z0.B, P0/M, Z31.B + movprfx z0.h, p0/z, z0.h + MOVPRFX Z0.H, P0/Z, Z0.H + movprfx z1.h, p0/z, z0.h + MOVPRFX Z1.H, P0/Z, Z0.H + movprfx z31.h, p0/z, z0.h + MOVPRFX Z31.H, P0/Z, Z0.H + movprfx z0.h, p2/z, z0.h + MOVPRFX Z0.H, P2/Z, Z0.H + movprfx z0.h, p7/z, z0.h + MOVPRFX Z0.H, P7/Z, Z0.H + movprfx z0.h, p0/z, z3.h + MOVPRFX Z0.H, P0/Z, Z3.H + movprfx z0.h, p0/z, z31.h + MOVPRFX Z0.H, P0/Z, Z31.H + movprfx z0.h, p0/m, z0.h + MOVPRFX Z0.H, P0/M, Z0.H + movprfx z1.h, p0/m, z0.h + MOVPRFX Z1.H, P0/M, Z0.H + movprfx z31.h, p0/m, z0.h + MOVPRFX Z31.H, P0/M, Z0.H + movprfx z0.h, p2/m, z0.h + MOVPRFX Z0.H, P2/M, Z0.H + movprfx z0.h, p7/m, z0.h + MOVPRFX Z0.H, P7/M, Z0.H + movprfx z0.h, p0/m, z3.h + MOVPRFX Z0.H, P0/M, Z3.H + movprfx z0.h, p0/m, z31.h + MOVPRFX Z0.H, P0/M, Z31.H + movprfx z0.s, p0/z, z0.s + MOVPRFX Z0.S, P0/Z, Z0.S + movprfx z1.s, p0/z, z0.s + MOVPRFX Z1.S, P0/Z, Z0.S + movprfx z31.s, p0/z, z0.s + MOVPRFX Z31.S, P0/Z, Z0.S + movprfx z0.s, p2/z, z0.s + MOVPRFX Z0.S, P2/Z, Z0.S + movprfx z0.s, p7/z, z0.s + MOVPRFX Z0.S, P7/Z, Z0.S + movprfx z0.s, p0/z, z3.s + MOVPRFX Z0.S, P0/Z, Z3.S + movprfx z0.s, p0/z, z31.s + MOVPRFX Z0.S, P0/Z, Z31.S + movprfx z0.s, p0/m, z0.s + MOVPRFX Z0.S, P0/M, Z0.S + movprfx z1.s, p0/m, z0.s + MOVPRFX Z1.S, P0/M, Z0.S + movprfx z31.s, p0/m, z0.s + MOVPRFX Z31.S, P0/M, Z0.S + movprfx z0.s, p2/m, z0.s + MOVPRFX Z0.S, P2/M, Z0.S + movprfx z0.s, p7/m, z0.s + MOVPRFX Z0.S, P7/M, Z0.S + movprfx z0.s, p0/m, z3.s + MOVPRFX Z0.S, P0/M, Z3.S + movprfx z0.s, p0/m, z31.s + MOVPRFX Z0.S, P0/M, Z31.S + movprfx z0.d, p0/z, z0.d + MOVPRFX Z0.D, P0/Z, Z0.D + movprfx z1.d, p0/z, z0.d + MOVPRFX Z1.D, P0/Z, Z0.D + movprfx z31.d, p0/z, z0.d + MOVPRFX Z31.D, P0/Z, Z0.D + movprfx z0.d, p2/z, z0.d + MOVPRFX Z0.D, P2/Z, Z0.D + movprfx z0.d, p7/z, z0.d + MOVPRFX Z0.D, P7/Z, Z0.D + movprfx z0.d, p0/z, z3.d + MOVPRFX Z0.D, P0/Z, Z3.D + movprfx z0.d, p0/z, z31.d + MOVPRFX Z0.D, P0/Z, Z31.D + movprfx z0.d, p0/m, z0.d + MOVPRFX Z0.D, P0/M, Z0.D + movprfx z1.d, p0/m, z0.d + MOVPRFX Z1.D, P0/M, Z0.D + movprfx z31.d, p0/m, z0.d + MOVPRFX Z31.D, P0/M, Z0.D + movprfx z0.d, p2/m, z0.d + MOVPRFX Z0.D, P2/M, Z0.D + movprfx z0.d, p7/m, z0.d + MOVPRFX Z0.D, P7/M, Z0.D + movprfx z0.d, p0/m, z3.d + MOVPRFX Z0.D, P0/M, Z3.D + movprfx z0.d, p0/m, z31.d + MOVPRFX Z0.D, P0/M, Z31.D diff --git a/gas/testsuite/gas/aarch64/sve.d b/gas/testsuite/gas/aarch64/sve.d index ff65f4e..5d6d756 100644 --- a/gas/testsuite/gas/aarch64/sve.d +++ b/gas/testsuite/gas/aarch64/sve.d @@ -23128,128 +23128,6 @@ Disassembly of section .*: [^:]+: 04c46000 mls z0.d, p0/m, z0.d, z4.d [^:]+: 04df6000 mls z0.d, p0/m, z0.d, z31.d [^:]+: 04df6000 mls z0.d, p0/m, z0.d, z31.d -[^:]+: 0420bc00 movprfx z0, z0 -[^:]+: 0420bc00 movprfx z0, z0 -[^:]+: 0420bc01 movprfx z1, z0 -[^:]+: 0420bc01 movprfx z1, z0 -[^:]+: 0420bc1f movprfx z31, z0 -[^:]+: 0420bc1f movprfx z31, z0 -[^:]+: 0420bc40 movprfx z0, z2 -[^:]+: 0420bc40 movprfx z0, z2 -[^:]+: 0420bfe0 movprfx z0, z31 -[^:]+: 0420bfe0 movprfx z0, z31 -[^:]+: 04102000 movprfx z0.b, p0/z, z0.b -[^:]+: 04102000 movprfx z0.b, p0/z, z0.b -[^:]+: 04102001 movprfx z1.b, p0/z, z0.b -[^:]+: 04102001 movprfx z1.b, p0/z, z0.b -[^:]+: 0410201f movprfx z31.b, p0/z, z0.b -[^:]+: 0410201f movprfx z31.b, p0/z, z0.b -[^:]+: 04102800 movprfx z0.b, p2/z, z0.b -[^:]+: 04102800 movprfx z0.b, p2/z, z0.b -[^:]+: 04103c00 movprfx z0.b, p7/z, z0.b -[^:]+: 04103c00 movprfx z0.b, p7/z, z0.b -[^:]+: 04102060 movprfx z0.b, p0/z, z3.b -[^:]+: 04102060 movprfx z0.b, p0/z, z3.b -[^:]+: 041023e0 movprfx z0.b, p0/z, z31.b -[^:]+: 041023e0 movprfx z0.b, p0/z, z31.b -[^:]+: 04112000 movprfx z0.b, p0/m, z0.b -[^:]+: 04112000 movprfx z0.b, p0/m, z0.b -[^:]+: 04112001 movprfx z1.b, p0/m, z0.b -[^:]+: 04112001 movprfx z1.b, p0/m, z0.b -[^:]+: 0411201f movprfx z31.b, p0/m, z0.b -[^:]+: 0411201f movprfx z31.b, p0/m, z0.b -[^:]+: 04112800 movprfx z0.b, p2/m, z0.b -[^:]+: 04112800 movprfx z0.b, p2/m, z0.b -[^:]+: 04113c00 movprfx z0.b, p7/m, z0.b -[^:]+: 04113c00 movprfx z0.b, p7/m, z0.b -[^:]+: 04112060 movprfx z0.b, p0/m, z3.b -[^:]+: 04112060 movprfx z0.b, p0/m, z3.b -[^:]+: 041123e0 movprfx z0.b, p0/m, z31.b -[^:]+: 041123e0 movprfx z0.b, p0/m, z31.b -[^:]+: 04502000 movprfx z0.h, p0/z, z0.h -[^:]+: 04502000 movprfx z0.h, p0/z, z0.h -[^:]+: 04502001 movprfx z1.h, p0/z, z0.h -[^:]+: 04502001 movprfx z1.h, p0/z, z0.h -[^:]+: 0450201f movprfx z31.h, p0/z, z0.h -[^:]+: 0450201f movprfx z31.h, p0/z, z0.h -[^:]+: 04502800 movprfx z0.h, p2/z, z0.h -[^:]+: 04502800 movprfx z0.h, p2/z, z0.h -[^:]+: 04503c00 movprfx z0.h, p7/z, z0.h -[^:]+: 04503c00 movprfx z0.h, p7/z, z0.h -[^:]+: 04502060 movprfx z0.h, p0/z, z3.h -[^:]+: 04502060 movprfx z0.h, p0/z, z3.h -[^:]+: 045023e0 movprfx z0.h, p0/z, z31.h -[^:]+: 045023e0 movprfx z0.h, p0/z, z31.h -[^:]+: 04512000 movprfx z0.h, p0/m, z0.h -[^:]+: 04512000 movprfx z0.h, p0/m, z0.h -[^:]+: 04512001 movprfx z1.h, p0/m, z0.h -[^:]+: 04512001 movprfx z1.h, p0/m, z0.h -[^:]+: 0451201f movprfx z31.h, p0/m, z0.h -[^:]+: 0451201f movprfx z31.h, p0/m, z0.h -[^:]+: 04512800 movprfx z0.h, p2/m, z0.h -[^:]+: 04512800 movprfx z0.h, p2/m, z0.h -[^:]+: 04513c00 movprfx z0.h, p7/m, z0.h -[^:]+: 04513c00 movprfx z0.h, p7/m, z0.h -[^:]+: 04512060 movprfx z0.h, p0/m, z3.h -[^:]+: 04512060 movprfx z0.h, p0/m, z3.h -[^:]+: 045123e0 movprfx z0.h, p0/m, z31.h -[^:]+: 045123e0 movprfx z0.h, p0/m, z31.h -[^:]+: 04902000 movprfx z0.s, p0/z, z0.s -[^:]+: 04902000 movprfx z0.s, p0/z, z0.s -[^:]+: 04902001 movprfx z1.s, p0/z, z0.s -[^:]+: 04902001 movprfx z1.s, p0/z, z0.s -[^:]+: 0490201f movprfx z31.s, p0/z, z0.s -[^:]+: 0490201f movprfx z31.s, p0/z, z0.s -[^:]+: 04902800 movprfx z0.s, p2/z, z0.s -[^:]+: 04902800 movprfx z0.s, p2/z, z0.s -[^:]+: 04903c00 movprfx z0.s, p7/z, z0.s -[^:]+: 04903c00 movprfx z0.s, p7/z, z0.s -[^:]+: 04902060 movprfx z0.s, p0/z, z3.s -[^:]+: 04902060 movprfx z0.s, p0/z, z3.s -[^:]+: 049023e0 movprfx z0.s, p0/z, z31.s -[^:]+: 049023e0 movprfx z0.s, p0/z, z31.s -[^:]+: 04912000 movprfx z0.s, p0/m, z0.s -[^:]+: 04912000 movprfx z0.s, p0/m, z0.s -[^:]+: 04912001 movprfx z1.s, p0/m, z0.s -[^:]+: 04912001 movprfx z1.s, p0/m, z0.s -[^:]+: 0491201f movprfx z31.s, p0/m, z0.s -[^:]+: 0491201f movprfx z31.s, p0/m, z0.s -[^:]+: 04912800 movprfx z0.s, p2/m, z0.s -[^:]+: 04912800 movprfx z0.s, p2/m, z0.s -[^:]+: 04913c00 movprfx z0.s, p7/m, z0.s -[^:]+: 04913c00 movprfx z0.s, p7/m, z0.s -[^:]+: 04912060 movprfx z0.s, p0/m, z3.s -[^:]+: 04912060 movprfx z0.s, p0/m, z3.s -[^:]+: 049123e0 movprfx z0.s, p0/m, z31.s -[^:]+: 049123e0 movprfx z0.s, p0/m, z31.s -[^:]+: 04d02000 movprfx z0.d, p0/z, z0.d -[^:]+: 04d02000 movprfx z0.d, p0/z, z0.d -[^:]+: 04d02001 movprfx z1.d, p0/z, z0.d -[^:]+: 04d02001 movprfx z1.d, p0/z, z0.d -[^:]+: 04d0201f movprfx z31.d, p0/z, z0.d -[^:]+: 04d0201f movprfx z31.d, p0/z, z0.d -[^:]+: 04d02800 movprfx z0.d, p2/z, z0.d -[^:]+: 04d02800 movprfx z0.d, p2/z, z0.d -[^:]+: 04d03c00 movprfx z0.d, p7/z, z0.d -[^:]+: 04d03c00 movprfx z0.d, p7/z, z0.d -[^:]+: 04d02060 movprfx z0.d, p0/z, z3.d -[^:]+: 04d02060 movprfx z0.d, p0/z, z3.d -[^:]+: 04d023e0 movprfx z0.d, p0/z, z31.d -[^:]+: 04d023e0 movprfx z0.d, p0/z, z31.d -[^:]+: 04d12000 movprfx z0.d, p0/m, z0.d -[^:]+: 04d12000 movprfx z0.d, p0/m, z0.d -[^:]+: 04d12001 movprfx z1.d, p0/m, z0.d -[^:]+: 04d12001 movprfx z1.d, p0/m, z0.d -[^:]+: 04d1201f movprfx z31.d, p0/m, z0.d -[^:]+: 04d1201f movprfx z31.d, p0/m, z0.d -[^:]+: 04d12800 movprfx z0.d, p2/m, z0.d -[^:]+: 04d12800 movprfx z0.d, p2/m, z0.d -[^:]+: 04d13c00 movprfx z0.d, p7/m, z0.d -[^:]+: 04d13c00 movprfx z0.d, p7/m, z0.d -[^:]+: 04d12060 movprfx z0.d, p0/m, z3.d -[^:]+: 04d12060 movprfx z0.d, p0/m, z3.d -[^:]+: 04d123e0 movprfx z0.d, p0/m, z31.d -[^:]+: 04d123e0 movprfx z0.d, p0/m, z31.d [^:]+: 040+e000 msb z0.b, p0/m, z0.b, z0.b [^:]+: 040+e000 msb z0.b, p0/m, z0.b, z0.b [^:]+: 040+e001 msb z1.b, p0/m, z0.b, z0.b diff --git a/gas/testsuite/gas/aarch64/sve.s b/gas/testsuite/gas/aarch64/sve.s index 3dbf486..f3ca5e8 100644 --- a/gas/testsuite/gas/aarch64/sve.s +++ b/gas/testsuite/gas/aarch64/sve.s @@ -23137,128 +23137,6 @@ MLS Z0.D, P0/M, Z0.D, Z4.D mls z0.d, p0/m, z0.d, z31.d MLS Z0.D, P0/M, Z0.D, Z31.D - movprfx z0, z0 - MOVPRFX Z0, Z0 - movprfx z1, z0 - MOVPRFX Z1, Z0 - movprfx z31, z0 - MOVPRFX Z31, Z0 - movprfx z0, z2 - MOVPRFX Z0, Z2 - movprfx z0, z31 - MOVPRFX Z0, Z31 - movprfx z0.b, p0/z, z0.b - MOVPRFX Z0.B, P0/Z, Z0.B - movprfx z1.b, p0/z, z0.b - MOVPRFX Z1.B, P0/Z, Z0.B - movprfx z31.b, p0/z, z0.b - MOVPRFX Z31.B, P0/Z, Z0.B - movprfx z0.b, p2/z, z0.b - MOVPRFX Z0.B, P2/Z, Z0.B - movprfx z0.b, p7/z, z0.b - MOVPRFX Z0.B, P7/Z, Z0.B - movprfx z0.b, p0/z, z3.b - MOVPRFX Z0.B, P0/Z, Z3.B - movprfx z0.b, p0/z, z31.b - MOVPRFX Z0.B, P0/Z, Z31.B - movprfx z0.b, p0/m, z0.b - MOVPRFX Z0.B, P0/M, Z0.B - movprfx z1.b, p0/m, z0.b - MOVPRFX Z1.B, P0/M, Z0.B - movprfx z31.b, p0/m, z0.b - MOVPRFX Z31.B, P0/M, Z0.B - movprfx z0.b, p2/m, z0.b - MOVPRFX Z0.B, P2/M, Z0.B - movprfx z0.b, p7/m, z0.b - MOVPRFX Z0.B, P7/M, Z0.B - movprfx z0.b, p0/m, z3.b - MOVPRFX Z0.B, P0/M, Z3.B - movprfx z0.b, p0/m, z31.b - MOVPRFX Z0.B, P0/M, Z31.B - movprfx z0.h, p0/z, z0.h - MOVPRFX Z0.H, P0/Z, Z0.H - movprfx z1.h, p0/z, z0.h - MOVPRFX Z1.H, P0/Z, Z0.H - movprfx z31.h, p0/z, z0.h - MOVPRFX Z31.H, P0/Z, Z0.H - movprfx z0.h, p2/z, z0.h - MOVPRFX Z0.H, P2/Z, Z0.H - movprfx z0.h, p7/z, z0.h - MOVPRFX Z0.H, P7/Z, Z0.H - movprfx z0.h, p0/z, z3.h - MOVPRFX Z0.H, P0/Z, Z3.H - movprfx z0.h, p0/z, z31.h - MOVPRFX Z0.H, P0/Z, Z31.H - movprfx z0.h, p0/m, z0.h - MOVPRFX Z0.H, P0/M, Z0.H - movprfx z1.h, p0/m, z0.h - MOVPRFX Z1.H, P0/M, Z0.H - movprfx z31.h, p0/m, z0.h - MOVPRFX Z31.H, P0/M, Z0.H - movprfx z0.h, p2/m, z0.h - MOVPRFX Z0.H, P2/M, Z0.H - movprfx z0.h, p7/m, z0.h - MOVPRFX Z0.H, P7/M, Z0.H - movprfx z0.h, p0/m, z3.h - MOVPRFX Z0.H, P0/M, Z3.H - movprfx z0.h, p0/m, z31.h - MOVPRFX Z0.H, P0/M, Z31.H - movprfx z0.s, p0/z, z0.s - MOVPRFX Z0.S, P0/Z, Z0.S - movprfx z1.s, p0/z, z0.s - MOVPRFX Z1.S, P0/Z, Z0.S - movprfx z31.s, p0/z, z0.s - MOVPRFX Z31.S, P0/Z, Z0.S - movprfx z0.s, p2/z, z0.s - MOVPRFX Z0.S, P2/Z, Z0.S - movprfx z0.s, p7/z, z0.s - MOVPRFX Z0.S, P7/Z, Z0.S - movprfx z0.s, p0/z, z3.s - MOVPRFX Z0.S, P0/Z, Z3.S - movprfx z0.s, p0/z, z31.s - MOVPRFX Z0.S, P0/Z, Z31.S - movprfx z0.s, p0/m, z0.s - MOVPRFX Z0.S, P0/M, Z0.S - movprfx z1.s, p0/m, z0.s - MOVPRFX Z1.S, P0/M, Z0.S - movprfx z31.s, p0/m, z0.s - MOVPRFX Z31.S, P0/M, Z0.S - movprfx z0.s, p2/m, z0.s - MOVPRFX Z0.S, P2/M, Z0.S - movprfx z0.s, p7/m, z0.s - MOVPRFX Z0.S, P7/M, Z0.S - movprfx z0.s, p0/m, z3.s - MOVPRFX Z0.S, P0/M, Z3.S - movprfx z0.s, p0/m, z31.s - MOVPRFX Z0.S, P0/M, Z31.S - movprfx z0.d, p0/z, z0.d - MOVPRFX Z0.D, P0/Z, Z0.D - movprfx z1.d, p0/z, z0.d - MOVPRFX Z1.D, P0/Z, Z0.D - movprfx z31.d, p0/z, z0.d - MOVPRFX Z31.D, P0/Z, Z0.D - movprfx z0.d, p2/z, z0.d - MOVPRFX Z0.D, P2/Z, Z0.D - movprfx z0.d, p7/z, z0.d - MOVPRFX Z0.D, P7/Z, Z0.D - movprfx z0.d, p0/z, z3.d - MOVPRFX Z0.D, P0/Z, Z3.D - movprfx z0.d, p0/z, z31.d - MOVPRFX Z0.D, P0/Z, Z31.D - movprfx z0.d, p0/m, z0.d - MOVPRFX Z0.D, P0/M, Z0.D - movprfx z1.d, p0/m, z0.d - MOVPRFX Z1.D, P0/M, Z0.D - movprfx z31.d, p0/m, z0.d - MOVPRFX Z31.D, P0/M, Z0.D - movprfx z0.d, p2/m, z0.d - MOVPRFX Z0.D, P2/M, Z0.D - movprfx z0.d, p7/m, z0.d - MOVPRFX Z0.D, P7/M, Z0.D - movprfx z0.d, p0/m, z3.d - MOVPRFX Z0.D, P0/M, Z3.D - movprfx z0.d, p0/m, z31.d - MOVPRFX Z0.D, P0/M, Z31.D msb z0.b, p0/m, z0.b, z0.b MSB Z0.B, P0/M, Z0.B, Z0.B msb z1.b, p0/m, z0.b, z0.b diff --git a/gas/testsuite/gas/aarch64/sysreg-diagnostic.d b/gas/testsuite/gas/aarch64/sysreg-diagnostic.d index 8389473..fb39db2 100644 --- a/gas/testsuite/gas/aarch64/sysreg-diagnostic.d +++ b/gas/testsuite/gas/aarch64/sysreg-diagnostic.d @@ -11,4 +11,4 @@ Disassembly of section \.text: .*: d5130503 msr dbgdtrtx_el0, x3 .*: d5330503 mrs x3, dbgdtrrx_el0 .*: d5330503 mrs x3, dbgdtrrx_el0 -.*: d5180003 msr midr_el1, x3 ; note: writing to a read-only register\. +.*: d5180003 msr midr_el1, x3 // note: writing to a read-only register diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2600d6c..36c5af2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,14 @@ 2018-10-03 Tamar Christina + * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier. + * aarch64-dis.c (print_operands): Refactor to take notes. + (print_verifier_notes): New. + (print_aarch64_insn): Apply constraint verifier. + (print_insn_aarch64_word): Update call to print_aarch64_insn. + * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format. + +2018-10-03 Tamar Christina + * aarch64-opc.c (init_insn_block): New. (verify_constraints, aarch64_is_destructive_by_operands): New. * aarch64-opc.h (verify_constraints): New. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 35704cd..b865d50 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1949,7 +1949,7 @@ aarch64_opcode_encode (const aarch64_opcode *opcode, const aarch64_inst *inst_ori, aarch64_insn *code, aarch64_opnd_qualifier_t *qlf_seq, aarch64_operand_error *mismatch_detail, - aarch64_instr_sequence* insn_sequence ATTRIBUTE_UNUSED) + aarch64_instr_sequence* insn_sequence) { int i; const aarch64_opcode *aliased; @@ -2036,6 +2036,38 @@ aarch64_opcode_encode (const aarch64_opcode *opcode, variant. */ aarch64_encode_variant_using_iclass (inst); + /* Run a verifier if the instruction has one set. */ + if (opcode->verifier) + { + enum err_type result = opcode->verifier (inst, *code, 0, TRUE, + mismatch_detail, insn_sequence); + switch (result) + { + case ERR_UND: + case ERR_UNP: + case ERR_NYI: + return FALSE; + default: + break; + } + } + + /* Always run constrain verifiers, this is needed because constrains need to + maintain a global state. Regardless if the instruction has the flag set + or not. */ + enum err_type result = verify_constraints (inst, *code, 0, TRUE, + mismatch_detail, insn_sequence); + switch (result) + { + case ERR_UND: + case ERR_UNP: + case ERR_NYI: + return FALSE; + default: + break; + } + + encoding_exit: DEBUG_TRACE ("exit with %s", opcode->name); diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 373ddae..c9bd4ae 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -45,7 +45,7 @@ static int no_aliases = 0; /* If set disassemble as most general inst. */ output as comments. */ /* Currently active instruction sequence. */ -static aarch64_instr_sequence insn_sequence ATTRIBUTE_UNUSED; +static aarch64_instr_sequence insn_sequence; static void set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED) @@ -2983,10 +2983,11 @@ aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst, static void print_operands (bfd_vma pc, const aarch64_opcode *opcode, - const aarch64_opnd_info *opnds, struct disassemble_info *info) + const aarch64_opnd_info *opnds, struct disassemble_info *info, + bfd_boolean *has_notes) { - int i, pcrel_p, num_printed; char *notes = NULL; + int i, pcrel_p, num_printed; for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; ++i) { char str[128]; @@ -3016,7 +3017,10 @@ print_operands (bfd_vma pc, const aarch64_opcode *opcode, } if (notes && !no_notes) - (*info->fprintf_func) (info->stream, "\t; note: %s", notes); + { + *has_notes = TRUE; + (*info->fprintf_func) (info->stream, " // note: %s", notes); + } } /* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */ @@ -3074,15 +3078,63 @@ print_comment (const aarch64_inst *inst, struct disassemble_info *info) } } +/* Build notes from verifiers into a string for printing. */ + +static void +print_verifier_notes (aarch64_operand_error *detail, + struct disassemble_info *info) +{ + if (no_notes) + return; + + /* The output of the verifier cannot be a fatal error, otherwise the assembly + would not have succeeded. We can safely ignore these. */ + assert (detail->non_fatal); + assert (detail->error); + + /* If there are multiple verifier messages, concat them up to 1k. */ + (*info->fprintf_func) (info->stream, " // note: %s", detail->error); + if (detail->index >= 0) + (*info->fprintf_func) (info->stream, " at operand %d", detail->index + 1); +} + /* Print the instruction according to *INST. */ static void print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst, - struct disassemble_info *info) + const aarch64_insn code, + struct disassemble_info *info, + aarch64_operand_error *mismatch_details) { + bfd_boolean has_notes = FALSE; + print_mnemonic_name (inst, info); - print_operands (pc, inst->opcode, inst->operands, info); + print_operands (pc, inst->opcode, inst->operands, info, &has_notes); print_comment (inst, info); + + /* We've already printed a note, not enough space to print more so exit. + Usually notes shouldn't overlap so it shouldn't happen that we have a note + from a register and instruction at the same time. */ + if (has_notes) + return; + + /* Always run constraint verifiers, this is needed because constraints need to + maintain a global state regardless of whether the instruction has the flag + set or not. */ + enum err_type result = verify_constraints (inst, code, pc, FALSE, + mismatch_details, &insn_sequence); + switch (result) + { + case ERR_UND: + case ERR_UNP: + case ERR_NYI: + assert (0); + case ERR_VFI: + print_verifier_notes (mismatch_details, info); + break; + default: + break; + } } /* Entry-point of the instruction disassembler and printer. */ @@ -3139,7 +3191,7 @@ print_insn_aarch64_word (bfd_vma pc, break; case ERR_OK: user_friendly_fixup (&inst); - print_aarch64_insn (pc, &inst, info); + print_aarch64_insn (pc, &inst, word, info, errors); break; default: abort (); diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index c28cac4..3f62e2a 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3052,7 +3052,7 @@ void aarch64_print_operand (char *buf, size_t size, bfd_vma pc, const aarch64_opcode *opcode, const aarch64_opnd_info *opnds, int idx, int *pcrel_p, - bfd_vma *address, char** notes ATTRIBUTE_UNUSED) + bfd_vma *address, char** notes) { unsigned int i, num_conds; const char *name = NULL; @@ -3600,9 +3600,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, F_REG_READ is there, that means we were looking for a write register. See aarch64_ext_sysreg. */ if (aarch64_sys_regs[i].flags & F_REG_WRITE) - *notes = _("reading from a write-only register."); + *notes = _("reading from a write-only register"); else if (aarch64_sys_regs[i].flags & F_REG_READ) - *notes = _("writing to a read-only register."); + *notes = _("writing to a read-only register"); } } -- 2.7.4