From bdd1eba37b64e64c2d93d3e79223b5933d631447 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Sat, 12 Sep 2020 22:39:39 +0200 Subject: [PATCH] [ARM] Add additional vecreduce float legalization test (NFC) --- .../ARM/vecreduce-fadd-legalization-soft-float.ll | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll b/llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll index f3eeb11..164cfe1 100644 --- a/llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll +++ b/llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll @@ -1,10 +1,49 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK +declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half, <4 x half>) declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x float>) declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double, <2 x double>) declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128, <2 x fp128>) +define half @test_v4f16(<4 x half> %a) nounwind { +; CHECK-LABEL: test_v4f16: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr} +; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr} +; CHECK-NEXT: mov r7, #255 +; CHECK-NEXT: mov r6, r0 +; CHECK-NEXT: orr r7, r7, #65280 +; CHECK-NEXT: mov r4, r3 +; CHECK-NEXT: and r0, r1, r7 +; CHECK-NEXT: mov r5, r2 +; CHECK-NEXT: bl __aeabi_h2f +; CHECK-NEXT: mov r8, r0 +; CHECK-NEXT: and r0, r4, r7 +; CHECK-NEXT: bl __aeabi_h2f +; CHECK-NEXT: mov r4, r0 +; CHECK-NEXT: and r0, r6, r7 +; CHECK-NEXT: bl __aeabi_h2f +; CHECK-NEXT: mov r6, r0 +; CHECK-NEXT: and r0, r5, r7 +; CHECK-NEXT: bl __aeabi_h2f +; CHECK-NEXT: mov r1, r0 +; CHECK-NEXT: mov r0, r6 +; CHECK-NEXT: bl __aeabi_fadd +; CHECK-NEXT: mov r5, r0 +; CHECK-NEXT: mov r0, r8 +; CHECK-NEXT: mov r1, r4 +; CHECK-NEXT: bl __aeabi_fadd +; CHECK-NEXT: mov r1, r0 +; CHECK-NEXT: mov r0, r5 +; CHECK-NEXT: bl __aeabi_fadd +; CHECK-NEXT: bl __aeabi_f2h +; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr} +; CHECK-NEXT: mov pc, lr + %b = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half 0.0, <4 x half> %a) + ret half %b +} + define float @test_v4f32(<4 x float> %a) nounwind { ; CHECK-LABEL: test_v4f32: ; CHECK: @ %bb.0: -- 2.7.4