From bdae564d1c6f8ce6f0b5dc0ed16aff41416725a0 Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 28 Jun 2023 15:02:38 +0100 Subject: [PATCH] [ARM][AArch64] !cast("XYZ") -> XYZ. NFC --- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 36 ++++++++++++++--------------- llvm/lib/Target/ARM/ARMInstrNEON.td | 21 ++++++++--------- 2 files changed, 27 insertions(+), 30 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 973b90a..ec5f840 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -4314,24 +4314,24 @@ defm : FPToIntegerPats; let Predicates = [HasFullFP16] in { def : Pat<(i32 (any_lround f16:$Rn)), - (!cast(FCVTASUWHr) f16:$Rn)>; + (FCVTASUWHr f16:$Rn)>; def : Pat<(i64 (any_lround f16:$Rn)), - (!cast(FCVTASUXHr) f16:$Rn)>; + (FCVTASUXHr f16:$Rn)>; def : Pat<(i64 (any_llround f16:$Rn)), - (!cast(FCVTASUXHr) f16:$Rn)>; + (FCVTASUXHr f16:$Rn)>; } def : Pat<(i32 (any_lround f32:$Rn)), - (!cast(FCVTASUWSr) f32:$Rn)>; + (FCVTASUWSr f32:$Rn)>; def : Pat<(i32 (any_lround f64:$Rn)), - (!cast(FCVTASUWDr) f64:$Rn)>; + (FCVTASUWDr f64:$Rn)>; def : Pat<(i64 (any_lround f32:$Rn)), - (!cast(FCVTASUXSr) f32:$Rn)>; + (FCVTASUXSr f32:$Rn)>; def : Pat<(i64 (any_lround f64:$Rn)), - (!cast(FCVTASUXDr) f64:$Rn)>; + (FCVTASUXDr f64:$Rn)>; def : Pat<(i64 (any_llround f32:$Rn)), - (!cast(FCVTASUXSr) f32:$Rn)>; + (FCVTASUXSr f32:$Rn)>; def : Pat<(i64 (any_llround f64:$Rn)), - (!cast(FCVTASUXDr) f64:$Rn)>; + (FCVTASUXDr f64:$Rn)>; //===----------------------------------------------------------------------===// // Scaled integer to floating point conversion instructions. @@ -4406,24 +4406,24 @@ let Predicates = [HasFRInt3264] in { // in the FCVTZS as the output of FRINTX is an integer). let Predicates = [HasFullFP16] in { def : Pat<(i32 (any_lrint f16:$Rn)), - (FCVTZSUWHr (!cast(FRINTXHr) f16:$Rn))>; + (FCVTZSUWHr (FRINTXHr f16:$Rn))>; def : Pat<(i64 (any_lrint f16:$Rn)), - (FCVTZSUXHr (!cast(FRINTXHr) f16:$Rn))>; + (FCVTZSUXHr (FRINTXHr f16:$Rn))>; def : Pat<(i64 (any_llrint f16:$Rn)), - (FCVTZSUXHr (!cast(FRINTXHr) f16:$Rn))>; + (FCVTZSUXHr (FRINTXHr f16:$Rn))>; } def : Pat<(i32 (any_lrint f32:$Rn)), - (FCVTZSUWSr (!cast(FRINTXSr) f32:$Rn))>; + (FCVTZSUWSr (FRINTXSr f32:$Rn))>; def : Pat<(i32 (any_lrint f64:$Rn)), - (FCVTZSUWDr (!cast(FRINTXDr) f64:$Rn))>; + (FCVTZSUWDr (FRINTXDr f64:$Rn))>; def : Pat<(i64 (any_lrint f32:$Rn)), - (FCVTZSUXSr (!cast(FRINTXSr) f32:$Rn))>; + (FCVTZSUXSr (FRINTXSr f32:$Rn))>; def : Pat<(i64 (any_lrint f64:$Rn)), - (FCVTZSUXDr (!cast(FRINTXDr) f64:$Rn))>; + (FCVTZSUXDr (FRINTXDr f64:$Rn))>; def : Pat<(i64 (any_llrint f32:$Rn)), - (FCVTZSUXSr (!cast(FRINTXSr) f32:$Rn))>; + (FCVTZSUXSr (FRINTXSr f32:$Rn))>; def : Pat<(i64 (any_llrint f64:$Rn)), - (FCVTZSUXDr (!cast(FRINTXDr) f64:$Rn))>; + (FCVTZSUXDr (FRINTXDr f64:$Rn))>; //===----------------------------------------------------------------------===// // Floating point two operand instructions. diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 4c8fe44..32c6843 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -7992,28 +7992,25 @@ multiclass Lengthen_HalfDouble_Big_Endian("extloadv" # SrcTy) addrmode6:$addr)), (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty) - (!cast("VREV16d8") - (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), + (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), - dsub_0)>, + dsub_0)>, Requires<[HasNEON]>; def _Z : Pat<(!cast("v" # DestLanes # DestTy) (!cast("zextloadv" # SrcTy) addrmode6:$addr)), (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty) - (!cast("VREV16d8") - (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), + (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), - dsub_0)>, + dsub_0)>, Requires<[HasNEON]>; def _S : Pat<(!cast("v" # DestLanes # DestTy) (!cast("sextloadv" # SrcTy) addrmode6:$addr)), (EXTRACT_SUBREG (!cast("VMOVLsv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLsv" # Insn1Lanes # Insn1Ty) - (!cast("VREV16d8") - (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), + (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), - dsub_0)>, + dsub_0)>, Requires<[HasNEON]>; } @@ -8066,17 +8063,17 @@ let Predicates = [HasNEON,IsLE] in { let Predicates = [HasNEON,IsBE] in { def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)), (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 - (!cast("VREV16d8") + (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>; def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)), (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 - (!cast("VREV16d8") + (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>; def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)), (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16 - (!cast("VREV16d8") + (VREV16d8 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>; } -- 2.7.4