From bd48def3e2203e534f8f7345664a35f08f1d9c32 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan <qiucofan@cn.ibm.com>
Date: Fri, 30 Apr 2021 12:02:37 +0800
Subject: [PATCH] Pre-commit test for PPC vector extraction test

---
 llvm/test/CodeGen/PowerPC/vec_extract_p9.ll   | 38 +++++++++++++++++++++++++++
 llvm/test/CodeGen/PowerPC/vec_extract_p9_2.ll | 12 +++++++++
 2 files changed, 50 insertions(+)

diff --git a/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll b/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
index 7e397f5..1ce1d41 100644
--- a/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
@@ -8,6 +8,7 @@ define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
@@ -25,6 +26,7 @@ define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    extsb 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
@@ -43,6 +45,7 @@ define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
@@ -62,6 +65,7 @@ define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsh 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
@@ -80,6 +84,7 @@ define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test5:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
@@ -98,6 +103,7 @@ define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test6:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
@@ -118,6 +124,7 @@ define zeroext i8 @test7(<16 x i8> %a) {
 ; CHECK-LE-NEXT:    vextubrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 1
@@ -137,6 +144,7 @@ define zeroext i16 @test8(<8 x i16> %a) {
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 2
@@ -155,6 +163,7 @@ define zeroext i32 @test9(<4 x i32> %a) {
 ; CHECK-LE-NEXT:    li 3, 12
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test9:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 12
@@ -165,3 +174,32 @@ entry:
   %vecext = extractelement <4 x i32> %a, i32 3
   ret i32 %vecext
 }
+
+define double @test10(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LE-LABEL: test10:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
+; CHECK-LE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
+; CHECK-LE-NEXT:    lxvx 36, 0, 3
+; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
+; CHECK-LE-NEXT:    lfs 1, .LCPI9_1@toc@l(3)
+; CHECK-LE-NEXT:    vperm 2, 2, 3, 4
+; CHECK-LE-NEXT:    xxswapd 0, 34
+; CHECK-LE-NEXT:    xsadddp 1, 0, 1
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: test10:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
+; CHECK-BE-NEXT:    vmrghw 3, 3, 2
+; CHECK-BE-NEXT:    lfs 0, .LCPI9_0@toc@l(3)
+; CHECK-BE-NEXT:    vmrglw 2, 3, 2
+; CHECK-BE-NEXT:    xsadddp 1, 34, 0
+; CHECK-BE-NEXT:    blr
+entry:
+  %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 2, i32 3, i32 7>
+  %cast = bitcast <4 x i32> %shuffle to <2 x double>
+  %extract = extractelement <2 x double> %cast, i32 0
+  %add = fadd double %extract, 1.0000
+  ret double %add
+}
diff --git a/llvm/test/CodeGen/PowerPC/vec_extract_p9_2.ll b/llvm/test/CodeGen/PowerPC/vec_extract_p9_2.ll
index 962996b..e12e06c 100644
--- a/llvm/test/CodeGen/PowerPC/vec_extract_p9_2.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_extract_p9_2.ll
@@ -9,6 +9,7 @@ define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) {
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test_add1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
@@ -31,6 +32,7 @@ define signext i8 @test_add2(<16 x i8> %a, i32 signext %index, i8 signext %c) {
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    extsb 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test_add2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
@@ -54,6 +56,7 @@ define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c)
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test_add3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
@@ -78,6 +81,7 @@ define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c)
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    extsh 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test_add4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
@@ -102,6 +106,7 @@ define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c)
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    clrldi 3, 3, 32
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test_add5:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
@@ -123,6 +128,7 @@ define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c)
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test_add6:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
@@ -142,6 +148,7 @@ define zeroext i32 @test7(<4 x i32> %a) {
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrwz 3, 34
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 8
@@ -159,6 +166,7 @@ define zeroext i32 @testadd_7(<4 x i32> %a, i32 zeroext %c) {
 ; CHECK-LE-NEXT:    add 3, 3, 5
 ; CHECK-LE-NEXT:    clrldi 3, 3, 32
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: testadd_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 8
@@ -178,6 +186,7 @@ define signext i32 @test8(<4 x i32> %a) {
 ; CHECK-LE-NEXT:    mfvsrwz 3, 34
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 8
@@ -196,6 +205,7 @@ define signext i32 @testadd_8(<4 x i32> %a, i32 signext %c) {
 ; CHECK-LE-NEXT:    add 3, 3, 5
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: testadd_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 8
@@ -217,6 +227,7 @@ define signext i32 @test9(<4 x i32> %a) {
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test9:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mfvsrwz 3, 34
@@ -235,6 +246,7 @@ define signext i32 @testadd_9(<4 x i32> %a, i32 signext %c) {
 ; CHECK-LE-NEXT:    add 3, 3, 5
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: testadd_9:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mfvsrwz 3, 34
-- 
2.7.4