From bceb7181c852f0829ff4b8b4c86bd949eceda7bf Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Mon, 25 Nov 2019 05:15:30 +0000 Subject: [PATCH] [rs6000] Refactor FP vector comparison operators This is a subsequent patch to refactor the existing float point vector comparison operator supports. The patch to fix PR92132 supplemented vector float point comparison by exposing the names for unordered/ordered/uneq/ltgt and adding ungt/unge/unlt/unle/ ne. As Segher pointed out, some patterns can be refactored together. The main link on this is: https://gcc.gnu.org/ml/gcc-patches/2019-11/msg00452.html gcc/ChangeLog 2019-11-25 Kewen Lin * config/rs6000/vector.md (vector_fp_comparison_simple): New code iterator. (vector_fp_comparison_complex): Likewise. (vector_ for VEC_F and vector_fp_comparison_simple): New define_and_split. (vector_ for VEC_F and vector_fp_comparison_complex): Likewise. (vector_lt for VEC_F): Refactor with vector_fp_comparison_simple. (vector_le for VEC_F): Likewise. (vector_unge for VEC_F): Likewise. (vector_unle for VEC_F): Likewise. (vector_ne for VEC_F): Likewise. (vector_ungt for VEC_F): Likewise. (vector_unlt for VEC_F): Likewise. (vector_ltgt for VEC_F): Refactor with vector_fp_comparison_complex. (vector_ordered for VEC_F): Likewise. (vector_uneq for VEC_F): Likewise. (vector_unordered for VEC_F): Likewise. From-SVN: r278665 --- gcc/ChangeLog | 23 ++++ gcc/config/rs6000/vector.md | 265 ++++++++++++++++++-------------------------- 2 files changed, 128 insertions(+), 160 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ca1527e..f37b986 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,26 @@ +2019-11-25 Kewen Lin + + * config/rs6000/vector.md (vector_fp_comparison_simple): New code + iterator. + (vector_fp_comparison_complex): Likewise. + (vector_ for VEC_F and vector_fp_comparison_simple): New + define_and_split. + (vector_ for VEC_F and vector_fp_comparison_complex): + Likewise. + (vector_lt for VEC_F): Refactor with + vector_fp_comparison_simple. + (vector_le for VEC_F): Likewise. + (vector_unge for VEC_F): Likewise. + (vector_unle for VEC_F): Likewise. + (vector_ne for VEC_F): Likewise. + (vector_ungt for VEC_F): Likewise. + (vector_unlt for VEC_F): Likewise. + (vector_ltgt for VEC_F): Refactor with + vector_fp_comparison_complex. + (vector_ordered for VEC_F): Likewise. + (vector_uneq for VEC_F): Likewise. + (vector_unordered for VEC_F): Likewise. + 2019-11-24 Jerry DeLisle PR fortran/92100 diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index b132037..75c4a99 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -107,6 +107,12 @@ (smin "smin") (smax "smax")]) +;; code iterators and attributes for vector FP comparison operators: +(define_code_iterator + vector_fp_comparison_simple [lt le ne ungt unge unlt unle]) +(define_code_iterator + vector_fp_comparison_complex [ltgt uneq unordered ordered]) + ;; Vector move instructions. Little-endian VSX loads and stores require ;; special handling to circumvent "element endianness." @@ -665,88 +671,6 @@ DONE; }) -; lt(a,b) = gt(b,a) -(define_expand "vector_lt" - [(set (match_operand:VEC_F 0 "vfloat_operand") - (lt:VEC_F (match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")))] - "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" -{ - emit_insn (gen_vector_gt (operands[0], operands[2], operands[1])); - DONE; -}) - -; le(a,b) = ge(b,a) -(define_expand "vector_le" - [(set (match_operand:VEC_F 0 "vfloat_operand") - (le:VEC_F (match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")))] - "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" -{ - emit_insn (gen_vector_ge (operands[0], operands[2], operands[1])); - DONE; -}) - -; ne(a,b) = ~eq(a,b) -(define_expand "vector_ne" - [(set (match_operand:VEC_F 0 "vfloat_operand") - (ne:VEC_F (match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")))] - "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" -{ - emit_insn (gen_vector_eq (operands[0], operands[1], operands[2])); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); - DONE; -}) - -; unge(a,b) = ~gt(b,a) -(define_expand "vector_unge" - [(set (match_operand:VEC_F 0 "vfloat_operand") - (unge:VEC_F (match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")))] - "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" -{ - emit_insn (gen_vector_gt (operands[0], operands[2], operands[1])); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); - DONE; -}) - -; ungt(a,b) = ~ge(b,a) -(define_expand "vector_ungt" - [(set (match_operand:VEC_F 0 "vfloat_operand") - (ungt:VEC_F (match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")))] - "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" -{ - emit_insn (gen_vector_ge (operands[0], operands[2], operands[1])); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); - DONE; -}) - -; unle(a,b) = ~gt(a,b) -(define_expand "vector_unle" - [(set (match_operand:VEC_F 0 "vfloat_operand") - (unle:VEC_F (match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")))] - "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" -{ - emit_insn (gen_vector_gt (operands[0], operands[1], operands[2])); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); - DONE; -}) - -; unlt(a,b) = ~ge(a,b) -(define_expand "vector_unlt" - [(set (match_operand:VEC_F 0 "vfloat_operand") - (unlt:VEC_F (match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")))] - "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" -{ - emit_insn (gen_vector_ge (operands[0], operands[1], operands[2])); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); - DONE; -}) - (define_expand "vector_eq" [(set (match_operand:VEC_C 0 "vlogical_operand") (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand") @@ -761,13 +685,6 @@ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") -(define_expand "vector_ge" - [(set (match_operand:VEC_F 0 "vlogical_operand") - (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand") - (match_operand:VEC_F 2 "vlogical_operand")))] - "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" - "") - ; >= for integer vectors: swap operands and apply not-greater-than (define_expand "vector_nlt" [(set (match_operand:VEC_I 3 "vlogical_operand") @@ -829,88 +746,116 @@ operands[3] = gen_reg_rtx_and_attrs (operands[0]); }) -(define_insn_and_split "vector_uneq" - [(set (match_operand:VEC_F 0 "vfloat_operand") - (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")))] - "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" - "#" - "" - [(set (match_dup 3) - (gt:VEC_F (match_dup 1) - (match_dup 2))) - (set (match_dup 4) - (gt:VEC_F (match_dup 2) - (match_dup 1))) - (set (match_dup 0) - (and:VEC_F (not:VEC_F (match_dup 3)) - (not:VEC_F (match_dup 4))))] -{ - operands[3] = gen_reg_rtx (mode); - operands[4] = gen_reg_rtx (mode); -}) +; There are 14 possible vector FP comparison operators, gt and eq of them have +; been expanded above, so just support 12 remaining operators here. -(define_insn_and_split "vector_ltgt" - [(set (match_operand:VEC_F 0 "vfloat_operand") - (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")))] +; For ge: +(define_expand "vector_ge" + [(set (match_operand:VEC_F 0 "vlogical_operand") + (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand") + (match_operand:VEC_F 2 "vlogical_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" - "#" - "" - [(set (match_dup 3) - (gt:VEC_F (match_dup 1) - (match_dup 2))) - (set (match_dup 4) - (gt:VEC_F (match_dup 2) - (match_dup 1))) - (set (match_dup 0) - (ior:VEC_F (match_dup 3) - (match_dup 4)))] -{ - operands[3] = gen_reg_rtx (mode); - operands[4] = gen_reg_rtx (mode); -}) + "") -(define_insn_and_split "vector_ordered" +; For lt/le/ne/ungt/unge/unlt/unle: +; lt(a,b) = gt(b,a) +; le(a,b) = ge(b,a) +; unge(a,b) = ~lt(a,b) +; unle(a,b) = ~gt(a,b) +; ne(a,b) = ~eq(a,b) +; ungt(a,b) = ~le(a,b) +; unlt(a,b) = ~ge(a,b) +(define_insn_and_split "vector_" [(set (match_operand:VEC_F 0 "vfloat_operand") - (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")))] - "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + (vector_fp_comparison_simple:VEC_F + (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && can_create_pseudo_p ()" "#" - "" - [(set (match_dup 3) - (ge:VEC_F (match_dup 1) - (match_dup 2))) - (set (match_dup 4) - (ge:VEC_F (match_dup 2) - (match_dup 1))) - (set (match_dup 0) - (ior:VEC_F (match_dup 3) - (match_dup 4)))] + "&& can_create_pseudo_p ()" + [(pc)] { - operands[3] = gen_reg_rtx (mode); - operands[4] = gen_reg_rtx (mode); + enum rtx_code cond = ; + bool need_invert = false; + + if (cond == UNLE || cond == UNLT || cond == NE || cond == UNGE + || cond == UNGT) + { + cond = reverse_condition_maybe_unordered (cond); + need_invert = true; + } + + if (cond == LT || cond == LE) + { + cond = swap_condition (cond); + std::swap (operands[1], operands[2]); + } + + gcc_assert (cond == EQ || cond == GE || cond == GT); + + rtx comp = gen_rtx_fmt_ee (cond, mode, operands[1], operands[2]); + + if (need_invert) + { + rtx res = gen_reg_rtx (mode); + emit_insn (gen_rtx_SET (res, comp)); + emit_insn (gen_one_cmpl2 (operands[0], res)); + } + else + emit_insn (gen_rtx_SET (operands[0], comp)); + + DONE; }) -(define_insn_and_split "vector_unordered" +; For ltgt/uneq/ordered/unordered: +; ltgt: gt(a,b) | gt(b,a) +; uneq: ~(gt(a,b) | gt(b,a)) +; ordered: ge(a,b) | ge(b,a) +; unordered: ~(ge(a,b) | ge(b,a)) +(define_insn_and_split "vector_" [(set (match_operand:VEC_F 0 "vfloat_operand") - (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand") - (match_operand:VEC_F 2 "vfloat_operand")))] - "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + (vector_fp_comparison_complex:VEC_F + (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && can_create_pseudo_p ()" "#" - "" - [(set (match_dup 3) - (ge:VEC_F (match_dup 1) - (match_dup 2))) - (set (match_dup 4) - (ge:VEC_F (match_dup 2) - (match_dup 1))) - (set (match_dup 0) - (and:VEC_F (not:VEC_F (match_dup 3)) - (not:VEC_F (match_dup 4))))] + "&& can_create_pseudo_p ()" + [(pc)] { - operands[3] = gen_reg_rtx (mode); - operands[4] = gen_reg_rtx (mode); + enum rtx_code cond = ; + bool need_invert = false; + + if (cond == UNORDERED || cond == UNEQ) + { + cond = reverse_condition_maybe_unordered (cond); + need_invert = true; + } + + if (cond == LTGT) + cond = GT; + else if (cond == ORDERED) + cond = GE; + else + gcc_unreachable (); + + rtx comp1 = gen_rtx_fmt_ee (cond, mode, operands[1], operands[2]); + rtx res1 = gen_reg_rtx (mode); + emit_insn (gen_rtx_SET (res1, comp1)); + rtx comp2 = gen_rtx_fmt_ee (cond, mode, operands[2], operands[1]); + rtx res2 = gen_reg_rtx (mode); + emit_insn (gen_rtx_SET (res2, comp2)); + + if (need_invert) + { + rtx not1 = gen_rtx_fmt_e (NOT, mode, res1); + rtx not2 = gen_rtx_fmt_e (NOT, mode, res2); + rtx comp3 = gen_rtx_fmt_ee (AND, mode, not1, not2); + emit_insn (gen_rtx_SET (operands[0], comp3)); + } + else + emit_insn (gen_ior3 (operands[0], res1, res2)); + + DONE; }) ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask -- 2.7.4