From bce20afe0f563aa803bf1740985f1ef5d26d7a36 Mon Sep 17 00:00:00 2001 From: James Y Knight Date: Wed, 5 Aug 2015 17:00:30 +0000 Subject: [PATCH] [Sparc] Fix disassembly of popc instruction. And add tests. Patch by David Wiberg! llvm-svn: 244064 --- llvm/lib/Target/Sparc/SparcInstrInfo.td | 4 ++-- llvm/test/MC/Disassembler/Sparc/sparc-v9.txt | 4 ++++ llvm/test/MC/Sparc/sparcv9-instructions.s | 5 +++++ 3 files changed, 11 insertions(+), 2 deletions(-) create mode 100644 llvm/test/MC/Disassembler/Sparc/sparc-v9.txt diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 3b9e048..51b71f4 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -1221,8 +1221,8 @@ let Predicates = [HasV9] in { // the top 32-bits before using it. To do this clearing, we use a SRLri X,0. let rs1 = 0 in def POPCrr : F3_1<2, 0b101110, - (outs IntRegs:$dst), (ins IntRegs:$src), - "popc $src, $dst", []>, Requires<[HasV9]>; + (outs IntRegs:$rd), (ins IntRegs:$rs2), + "popc $rs2, $rd", []>, Requires<[HasV9]>; def : Pat<(ctpop i32:$src), (POPCrr (SRLri $src, 0))>; diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-v9.txt b/llvm/test/MC/Disassembler/Sparc/sparc-v9.txt new file mode 100644 index 0000000..b8ca01c --- /dev/null +++ b/llvm/test/MC/Disassembler/Sparc/sparc-v9.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux | FileCheck %s + +# CHECK: popc %g1, %g2 +0x85 0x70 0x00 0x01 diff --git a/llvm/test/MC/Sparc/sparcv9-instructions.s b/llvm/test/MC/Sparc/sparcv9-instructions.s index 37f4c8b..e2cb87e 100644 --- a/llvm/test/MC/Sparc/sparcv9-instructions.s +++ b/llvm/test/MC/Sparc/sparcv9-instructions.s @@ -21,3 +21,8 @@ ! V9: subxcc %g1, %g2, %g3 ! encoding: [0x86,0xe0,0x40,0x02] subccc %g1, %g2, %g3 + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: popc %g1, %g2 + ! V9: popc %g1, %g2 ! encoding: [0x85,0x70,0x00,0x01] + popc %g1, %g2 + -- 2.7.4