From bbdf22ce136a7f02a8bd6c7e646d12a7e10db18d Mon Sep 17 00:00:00 2001 From: Konstantin Seurer Date: Wed, 13 Apr 2022 21:02:55 +0200 Subject: [PATCH] radv: Fix barriers with cp dma We need to wait for cp dma if VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT are set. Closes: #5911 Fixes: 4b9bc4791b5 ("radv: only sync CP DMA for transfer operations or bottom pipe") Signed-off-by: Konstantin Seurer Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 8e0f149..8ab0b5a 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -8452,9 +8452,10 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfo *dep_inf /* Make sure CP DMA is idle because the driver might have performed a DMA operation for copying a * buffer (or a MSAA image using FMASK) or updated a buffer which is a transfer operation. */ - if (src_stage_mask & (VK_PIPELINE_STAGE_2_COPY_BIT | - VK_PIPELINE_STAGE_2_TRANSFER_BIT | - VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT)) + if (src_stage_mask & + (VK_PIPELINE_STAGE_2_COPY_BIT | VK_PIPELINE_STAGE_2_CLEAR_BIT | + VK_PIPELINE_STAGE_2_TRANSFER_BIT | VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT | + VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT)) si_cp_dma_wait_for_idle(cmd_buffer); cmd_buffer->state.flush_bits |= dst_flush_bits; -- 2.7.4