From bb71f7d25106b366a31ab74d8c03eeda99d6a64f Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Wed, 17 Jun 2015 20:29:33 +0000 Subject: [PATCH] [Hexagon] Adding a number of other tests for min/max instructions and loading i1s. llvm-svn: 239935 --- llvm/test/CodeGen/Hexagon/cext.ll | 16 +++++++++++ llvm/test/CodeGen/Hexagon/cexti16.ll | 16 +++++++++++ llvm/test/CodeGen/Hexagon/hwloop-lt.ll | 2 +- llvm/test/CodeGen/Hexagon/hwloop-lt1.ll | 2 +- llvm/test/CodeGen/Hexagon/loadi1-G0.ll | 43 +++++++++++++++++++++++++++++ llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll | 43 +++++++++++++++++++++++++++++ llvm/test/CodeGen/Hexagon/loadi1-v4.ll | 45 +++++++++++++++++++++++++++++++ llvm/test/CodeGen/Hexagon/loadi1.ll | 45 +++++++++++++++++++++++++++++++ llvm/test/CodeGen/Hexagon/maxd.ll | 9 +++++++ llvm/test/CodeGen/Hexagon/maxh.ll | 23 ++++++++++++++++ llvm/test/CodeGen/Hexagon/maxud.ll | 9 +++++++ llvm/test/CodeGen/Hexagon/maxuw.ll | 9 +++++++ llvm/test/CodeGen/Hexagon/maxw.ll | 9 +++++++ llvm/test/CodeGen/Hexagon/mind.ll | 9 +++++++ llvm/test/CodeGen/Hexagon/minu-zext-16.ll | 11 ++++++++ llvm/test/CodeGen/Hexagon/minu-zext-8.ll | 11 ++++++++ llvm/test/CodeGen/Hexagon/minud.ll | 9 +++++++ llvm/test/CodeGen/Hexagon/minuw.ll | 9 +++++++ llvm/test/CodeGen/Hexagon/minw.ll | 9 +++++++ 19 files changed, 327 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/Hexagon/cext.ll create mode 100644 llvm/test/CodeGen/Hexagon/cexti16.ll create mode 100644 llvm/test/CodeGen/Hexagon/loadi1-G0.ll create mode 100644 llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll create mode 100644 llvm/test/CodeGen/Hexagon/loadi1-v4.ll create mode 100644 llvm/test/CodeGen/Hexagon/loadi1.ll create mode 100644 llvm/test/CodeGen/Hexagon/maxd.ll create mode 100644 llvm/test/CodeGen/Hexagon/maxh.ll create mode 100644 llvm/test/CodeGen/Hexagon/maxud.ll create mode 100644 llvm/test/CodeGen/Hexagon/maxuw.ll create mode 100644 llvm/test/CodeGen/Hexagon/maxw.ll create mode 100644 llvm/test/CodeGen/Hexagon/mind.ll create mode 100644 llvm/test/CodeGen/Hexagon/minu-zext-16.ll create mode 100644 llvm/test/CodeGen/Hexagon/minu-zext-8.ll create mode 100644 llvm/test/CodeGen/Hexagon/minud.ll create mode 100644 llvm/test/CodeGen/Hexagon/minuw.ll create mode 100644 llvm/test/CodeGen/Hexagon/minw.ll diff --git a/llvm/test/CodeGen/Hexagon/cext.ll b/llvm/test/CodeGen/Hexagon/cext.ll new file mode 100644 index 0000000..6daba8c --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/cext.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: memub(r{{[0-9]+}}{{ *}}<<{{ *}}#1{{ *}}+{{ *}}##a) + +@a = external global [5 x [2 x i8]] + +define zeroext i8 @foo(i8 zeroext %l) nounwind readonly { +for.end: + %idxprom = zext i8 %l to i32 + %arrayidx1 = getelementptr inbounds [5 x [2 x i8]], [5 x [2 x i8]]* @a, i32 0, i32 %idxprom, i32 0 + %0 = load i8, i8* %arrayidx1, align 1 + %conv = zext i8 %0 to i32 + %mul = mul nsw i32 %conv, 20 + %conv2 = trunc i32 %mul to i8 + ret i8 %conv2 +} + diff --git a/llvm/test/CodeGen/Hexagon/cexti16.ll b/llvm/test/CodeGen/Hexagon/cexti16.ll new file mode 100644 index 0000000..465cfe4 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/cexti16.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: memuh(r{{[0-9]+}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##a) + +@a = external global [5 x [2 x i16]] + +define signext i16 @foo(i16 zeroext %l) nounwind readonly { +for.end: + %idxprom = zext i16 %l to i32 + %arrayidx1 = getelementptr inbounds [5 x [2 x i16]], [5 x [2 x i16]]* @a, i32 0, i32 %idxprom, i32 0 + %0 = load i16, i16* %arrayidx1, align 2 + %conv = zext i16 %0 to i32 + %mul = mul nsw i32 %conv, 20 + %conv2 = trunc i32 %mul to i16 + ret i16 %conv2 +} + diff --git a/llvm/test/CodeGen/Hexagon/hwloop-lt.ll b/llvm/test/CodeGen/Hexagon/hwloop-lt.ll index 7e2ad2a..8919f26 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-lt.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-lt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 < %s | FileCheck %s +; RUN: llc -march=hexagon -O3 < %s | FileCheck %s ; CHECK-LABEL: @test_pos1_ir_slt ; CHECK: loop0 diff --git a/llvm/test/CodeGen/Hexagon/hwloop-lt1.ll b/llvm/test/CodeGen/Hexagon/hwloop-lt1.ll index 16fe728..cf97fff 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-lt1.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-lt1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; RUN: llc -march=hexagon < %s | FileCheck %s ; Check that we generate a hardware loop instruction. ; CHECK: endloop0 diff --git a/llvm/test/CodeGen/Hexagon/loadi1-G0.ll b/llvm/test/CodeGen/Hexagon/loadi1-G0.ll new file mode 100644 index 0000000..1116341 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/loadi1-G0.ll @@ -0,0 +1,43 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-small-data-threshold=0 < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + + +@flag = external global i1 + + +; CHECK-NOT: CONST + +define i32 @test_sextloadi1_32() { +entry: + %0 = load i1, i1* @flag, align 4 + %1 = sext i1 %0 to i32 + ret i32 %1 +} + + + +define i16 @test_zextloadi1_16() { +entry: + %0 = load i1, i1* @flag, align 4 + %1 = zext i1 %0 to i16 + ret i16 %1 +} + + +define i32 @test_zextloadi1_32() { +entry: + %0 = load i1, i1* @flag, align 4 + %1 = zext i1 %0 to i32 + ret i32 %1 +} + + +define i64 @test_zextloadi1_64() { +entry: + %0 = load i1, i1* @flag, align 4 + %1 = zext i1 %0 to i64 + ret i64 %1 +} + + diff --git a/llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll b/llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll new file mode 100644 index 0000000..b7df1a1 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll @@ -0,0 +1,43 @@ +; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + + +@flag = external global i1 + + +; CHECK-NOT: CONST + +define i32 @test_sextloadi1_32() { +entry: + %0 = load i1, i1* @flag, align 4 + %1 = sext i1 %0 to i32 + ret i32 %1 +} + + + +define i16 @test_zextloadi1_16() { +entry: + %0 = load i1, i1* @flag, align 4 + %1 = zext i1 %0 to i16 + ret i16 %1 +} + + +define i32 @test_zextloadi1_32() { +entry: + %0 = load i1, i1* @flag, align 4 + %1 = zext i1 %0 to i32 + ret i32 %1 +} + + +define i64 @test_zextloadi1_64() { +entry: + %0 = load i1, i1* @flag, align 4 + %1 = zext i1 %0 to i64 + ret i64 %1 +} + + diff --git a/llvm/test/CodeGen/Hexagon/loadi1-v4.ll b/llvm/test/CodeGen/Hexagon/loadi1-v4.ll new file mode 100644 index 0000000..15b0560 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/loadi1-v4.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + + +@flag = external global i1 + + +define i32 @test_sextloadi1_32() { +entry: + %0 = load i1, i1* @flag, align 4 +; CHECK: memub + %1 = sext i1 %0 to i32 + ret i32 %1 +} + + + +define i16 @test_zextloadi1_16() { +entry: + %0 = load i1, i1* @flag, align 4 +; CHECK: memub + %1 = zext i1 %0 to i16 + ret i16 %1 +} + + +define i32 @test_zextloadi1_32() { +entry: + %0 = load i1, i1* @flag, align 4 +; CHECK: memub + %1 = zext i1 %0 to i32 + ret i32 %1 +} + + +define i64 @test_zextloadi1_64() { +entry: + %0 = load i1, i1* @flag, align 4 +; CHECK: memub + %1 = zext i1 %0 to i64 + ret i64 %1 +} + + diff --git a/llvm/test/CodeGen/Hexagon/loadi1.ll b/llvm/test/CodeGen/Hexagon/loadi1.ll new file mode 100644 index 0000000..38c1dfe --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/loadi1.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + + +@flag = external global i1 + + +define i32 @test_sextloadi1_32() { +entry: + %0 = load i1, i1* @flag, align 4 +; CHECK: memub + %1 = sext i1 %0 to i32 + ret i32 %1 +} + + + +define i16 @test_zextloadi1_16() { +entry: + %0 = load i1, i1* @flag, align 4 +; CHECK: memub + %1 = zext i1 %0 to i16 + ret i16 %1 +} + + +define i32 @test_zextloadi1_32() { +entry: + %0 = load i1, i1* @flag, align 4 +; CHECK: memub + %1 = zext i1 %0 to i32 + ret i32 %1 +} + + +define i64 @test_zextloadi1_64() { +entry: + %0 = load i1, i1* @flag, align 4 +; CHECK: memub + %1 = zext i1 %0 to i64 + ret i64 %1 +} + + diff --git a/llvm/test/CodeGen/Hexagon/maxd.ll b/llvm/test/CodeGen/Hexagon/maxd.ll new file mode 100644 index 0000000..7f237fd --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/maxd.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: max + +define i64 @f(i64 %src, i64 %maxval) nounwind readnone { +entry: + %cmp = icmp slt i64 %maxval, %src + %cond = select i1 %cmp, i64 %src, i64 %maxval + ret i64 %cond +} diff --git a/llvm/test/CodeGen/Hexagon/maxh.ll b/llvm/test/CodeGen/Hexagon/maxh.ll new file mode 100644 index 0000000..79b5e92 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/maxh.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; The result of max(half-word, half-word) is also half-word. +; Check that we are not producing a sign extend after the max. +; CHECK-NOT: sxth + +define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone { +entry: + %conv.i = zext i16 %arg1 to i32 + %conv1.i = zext i16 %arg2 to i32 + %sub.i = sub nsw i32 %conv.i, %conv1.i + %sext.i = shl i32 %sub.i, 16 + %cmp.i = icmp slt i32 %sext.i, 65536 + %0 = ashr exact i32 %sext.i, 16 + %conv7.i = select i1 %cmp.i, i32 1, i32 %0 + %cmp8.i = icmp sgt i32 %conv7.i, 4 + %conv7.op.i = add i32 %conv7.i, 65535 + %shl = shl i64 %arg0, 2 + %.mask = and i32 %conv7.op.i, 65535 + %1 = zext i32 %.mask to i64 + %conv = select i1 %cmp8.i, i64 3, i64 %1 + %or = or i64 %conv, %shl + ret i64 %or +} diff --git a/llvm/test/CodeGen/Hexagon/maxud.ll b/llvm/test/CodeGen/Hexagon/maxud.ll new file mode 100644 index 0000000..eca4fae --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/maxud.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: maxu + +define i64 @f(i64 %src, i64 %maxval) nounwind readnone { +entry: + %cmp = icmp ult i64 %maxval, %src + %cond = select i1 %cmp, i64 %src, i64 %maxval + ret i64 %cond +} diff --git a/llvm/test/CodeGen/Hexagon/maxuw.ll b/llvm/test/CodeGen/Hexagon/maxuw.ll new file mode 100644 index 0000000..0dba1f5 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/maxuw.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: maxu + +define i32 @f(i32 %src, i32 %maxval) nounwind readnone { +entry: + %cmp = icmp ult i32 %maxval, %src + %cond = select i1 %cmp, i32 %src, i32 %maxval + ret i32 %cond +} diff --git a/llvm/test/CodeGen/Hexagon/maxw.ll b/llvm/test/CodeGen/Hexagon/maxw.ll new file mode 100644 index 0000000..e66ca95 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/maxw.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: max + +define i32 @f(i32 %src, i32 %maxval) nounwind readnone { +entry: + %cmp = icmp slt i32 %maxval, %src + %cond = select i1 %cmp, i32 %src, i32 %maxval + ret i32 %cond +} diff --git a/llvm/test/CodeGen/Hexagon/mind.ll b/llvm/test/CodeGen/Hexagon/mind.ll new file mode 100644 index 0000000..610283d --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/mind.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: min + +define i64 @f(i64 %src, i64 %maxval) nounwind readnone { +entry: + %cmp = icmp sgt i64 %maxval, %src + %cond = select i1 %cmp, i64 %src, i64 %maxval + ret i64 %cond +} diff --git a/llvm/test/CodeGen/Hexagon/minu-zext-16.ll b/llvm/test/CodeGen/Hexagon/minu-zext-16.ll new file mode 100644 index 0000000..e27507d --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/minu-zext-16.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: minu + +define zeroext i16 @f(i16* noalias nocapture %src) nounwind readonly { +entry: + %arrayidx = getelementptr inbounds i16, i16* %src, i32 1 + %0 = load i16, i16* %arrayidx, align 1 + %cmp = icmp ult i16 %0, 32767 + %. = select i1 %cmp, i16 %0, i16 32767 + ret i16 %. +} diff --git a/llvm/test/CodeGen/Hexagon/minu-zext-8.ll b/llvm/test/CodeGen/Hexagon/minu-zext-8.ll new file mode 100644 index 0000000..15dc1a1 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/minu-zext-8.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: minu + +define zeroext i8 @f(i8* noalias nocapture %src) nounwind readonly { +entry: + %arrayidx = getelementptr inbounds i8, i8* %src, i32 1 + %0 = load i8, i8* %arrayidx, align 1 + %cmp = icmp ult i8 %0, 127 + %. = select i1 %cmp, i8 %0, i8 127 + ret i8 %. +} diff --git a/llvm/test/CodeGen/Hexagon/minud.ll b/llvm/test/CodeGen/Hexagon/minud.ll new file mode 100644 index 0000000..29e8100 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/minud.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: minu + +define i64 @f(i64 %src, i64 %maxval) nounwind readnone { +entry: + %cmp = icmp ugt i64 %maxval, %src + %cond = select i1 %cmp, i64 %src, i64 %maxval + ret i64 %cond +} diff --git a/llvm/test/CodeGen/Hexagon/minuw.ll b/llvm/test/CodeGen/Hexagon/minuw.ll new file mode 100644 index 0000000..a88d1e1 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/minuw.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: minu + +define i32 @f(i32 %src, i32 %maxval) nounwind readnone { +entry: + %cmp = icmp ugt i32 %maxval, %src + %cond = select i1 %cmp, i32 %src, i32 %maxval + ret i32 %cond +} diff --git a/llvm/test/CodeGen/Hexagon/minw.ll b/llvm/test/CodeGen/Hexagon/minw.ll new file mode 100644 index 0000000..5bfaae0 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/minw.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: min + +define i32 @f(i32 %src, i32 %maxval) nounwind readnone { +entry: + %cmp = icmp sgt i32 %maxval, %src + %cond = select i1 %cmp, i32 %src, i32 %maxval + ret i32 %cond +} -- 2.7.4