From bb71536f2841449252952ac4f759c1e0eca7e137 Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Mon, 23 Jul 2018 12:59:23 +0930 Subject: [PATCH] power9 mfupmc/mtupmc PR 23419 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended opcode variants for mtspr/mfspr encodings. --- opcodes/ChangeLog | 6 ++++++ opcodes/ppc-opc.c | 18 ++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 076af1f..9974d2f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2018-07-23 Alan Modra + + PR 23419 + * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended + opcode variants for mtspr/mfspr encodings. + 2018-07-20 Chenghua Xu Maciej W. Rozycki diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 4a0fca5..ba1bd3b 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -5900,6 +5900,18 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}}, {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}}, {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}}, +{"mfupmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}}, +{"mfupmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}}, +{"mfupmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}}, +{"mfupmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}}, +{"mfupmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}}, +{"mfupmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}}, {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}}, {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}}, {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}}, @@ -6243,6 +6255,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, +{"mtupmc1", XSPR(31,467,771), XSPR_MASK, POWER9, 0, {RS}}, +{"mtupmc2", XSPR(31,467,772), XSPR_MASK, POWER9, 0, {RS}}, +{"mtupmc3", XSPR(31,467,773), XSPR_MASK, POWER9, 0, {RS}}, +{"mtupmc4", XSPR(31,467,774), XSPR_MASK, POWER9, 0, {RS}}, +{"mtupmc5", XSPR(31,467,775), XSPR_MASK, POWER9, 0, {RS}}, +{"mtupmc6", XSPR(31,467,776), XSPR_MASK, POWER9, 0, {RS}}, {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}}, {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}}, {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}}, -- 2.7.4