From bafaa53c4daf3c17e89bcbf3ebb9190f52e755c9 Mon Sep 17 00:00:00 2001 From: Nirav Dave Date: Wed, 29 Nov 2017 18:06:13 +0000 Subject: [PATCH] [ARM][DAG] Revert Disable post-legalization store merge for ARM Partially reverting enabling of post-legalization store merge (r319036) for just ARM backend as it is causing incorrect code in some Thumb2 cases. llvm-svn: 319331 --- llvm/lib/Target/ARM/ARMISelLowering.h | 3 +++ llvm/test/CodeGen/ARM/fp16-promote.ll | 50 +++++++++++++---------------------- 2 files changed, 22 insertions(+), 31 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index a791e2e..01f101d 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -532,6 +532,9 @@ class VectorType; bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const override; + // Disable currently because of invalid merge. + bool mergeStoresAfterLegalization() const override { return false; } + bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override { // Do not merge to larger than i32. diff --git a/llvm/test/CodeGen/ARM/fp16-promote.ll b/llvm/test/CodeGen/ARM/fp16-promote.ll index da2a1df..257d99d 100644 --- a/llvm/test/CodeGen/ARM/fp16-promote.ll +++ b/llvm/test/CodeGen/ARM/fp16-promote.ll @@ -817,37 +817,25 @@ define void @test_fmuladd(half* %p, half* %q, half* %r) #0 { ; CHECK-ALL-LABEL: test_insertelement: ; CHECK-ALL: sub sp, sp, #8 - -; CHECK-VFP: and -; CHECK-VFP: mov -; CHECK-VFP: ldrd -; CHECK-VFP: orr -; CHECK-VFP: ldrh -; CHECK-VFP: stm -; CHECK-VFP: strh -; CHECK-VFP: ldm -; CHECK-VFP: stm - -; CHECK-NOVFP: ldrh -; CHECK-NOVFP: ldrh -; CHECK-NOVFP: ldrh -; CHECK-NOVFP: ldrh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: mov -; CHECK-NOVFP-DAG: ldrh -; CHECK-NOVFP-DAG: orr -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: ldrh -; CHECK-NOVFP-DAG: ldrh -; CHECK-NOVFP-DAG: ldrh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh - +; CHECK-ALL: ldrh +; CHECK-ALL: ldrh +; CHECK-ALL: ldrh +; CHECK-ALL: ldrh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: mov +; CHECK-ALL-DAG: ldrh +; CHECK-ALL-DAG: orr +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: ldrh +; CHECK-ALL-DAG: ldrh +; CHECK-ALL-DAG: ldrh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh ; CHECK-ALL: add sp, sp, #8 define void @test_insertelement(half* %p, <4 x half>* %q, i32 %i) #0 { %a = load half, half* %p, align 2 -- 2.7.4