From bac974278c5e5a3d6dea40d2d22cb36bcc487cee Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Sat, 3 Dec 2022 18:38:12 +0000 Subject: [PATCH] CodeGen/CommandFlags: Convert Optional to std::optional --- lld/Common/TargetOptionsCommandFlags.cpp | 2 +- lld/include/lld/Common/TargetOptionsCommandFlags.h | 3 +-- llvm/include/llvm/CodeGen/CommandFlags.h | 8 ++++---- llvm/include/llvm/ExecutionEngine/ExecutionEngine.h | 2 +- .../llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h | 6 +++--- llvm/include/llvm/LTO/Config.h | 2 +- llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h | 2 +- llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h | 4 ++-- llvm/include/llvm/MC/TargetRegistry.h | 15 +++++++-------- llvm/lib/CodeGen/CommandFlags.cpp | 14 ++------------ llvm/lib/LTO/LTOBackend.cpp | 2 +- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 8 ++++---- llvm/lib/Target/AArch64/AArch64TargetMachine.h | 6 +++--- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 +++--- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 4 ++-- llvm/lib/Target/AMDGPU/R600TargetMachine.cpp | 2 +- llvm/lib/Target/AMDGPU/R600TargetMachine.h | 2 +- llvm/lib/Target/ARC/ARCTargetMachine.cpp | 4 ++-- llvm/lib/Target/ARC/ARCTargetMachine.h | 2 +- llvm/lib/Target/ARM/ARMTargetMachine.cpp | 8 ++++---- llvm/lib/Target/ARM/ARMTargetMachine.h | 6 +++--- llvm/lib/Target/AVR/AVRTargetMachine.cpp | 4 ++-- llvm/lib/Target/AVR/AVRTargetMachine.h | 2 +- llvm/lib/Target/BPF/BPFTargetMachine.cpp | 4 ++-- llvm/lib/Target/BPF/BPFTargetMachine.h | 2 +- llvm/lib/Target/CSKY/CSKYTargetMachine.cpp | 2 +- llvm/lib/Target/CSKY/CSKYTargetMachine.h | 2 +- llvm/lib/Target/DirectX/DirectXTargetMachine.cpp | 2 +- llvm/lib/Target/DirectX/DirectXTargetMachine.h | 2 +- llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp | 4 ++-- llvm/lib/Target/Hexagon/HexagonTargetMachine.h | 2 +- llvm/lib/Target/Lanai/LanaiTargetMachine.cpp | 4 ++-- llvm/lib/Target/Lanai/LanaiTargetMachine.h | 2 +- llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp | 4 ++-- llvm/lib/Target/LoongArch/LoongArchTargetMachine.h | 2 +- llvm/lib/Target/M68k/M68kTargetMachine.cpp | 4 ++-- llvm/lib/Target/M68k/M68kTargetMachine.h | 2 +- llvm/lib/Target/MSP430/MSP430TargetMachine.cpp | 4 ++-- llvm/lib/Target/MSP430/MSP430TargetMachine.h | 2 +- llvm/lib/Target/Mips/MipsTargetMachine.cpp | 8 ++++---- llvm/lib/Target/Mips/MipsTargetMachine.h | 6 +++--- llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp | 6 +++--- llvm/lib/Target/NVPTX/NVPTXTargetMachine.h | 6 +++--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 4 ++-- llvm/lib/Target/PowerPC/PPCTargetMachine.h | 2 +- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 4 ++-- llvm/lib/Target/RISCV/RISCVTargetMachine.h | 2 +- llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp | 4 ++-- llvm/lib/Target/SPIRV/SPIRVTargetMachine.h | 2 +- llvm/lib/Target/Sparc/SparcTargetMachine.cpp | 10 +++++----- llvm/lib/Target/Sparc/SparcTargetMachine.h | 8 ++++---- llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp | 4 ++-- llvm/lib/Target/SystemZ/SystemZTargetMachine.h | 2 +- llvm/lib/Target/TargetMachineC.cpp | 2 +- llvm/lib/Target/VE/VETargetMachine.cpp | 4 ++-- llvm/lib/Target/VE/VETargetMachine.h | 5 +++-- llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp | 4 ++-- llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h | 2 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 7 +++---- llvm/lib/Target/X86/X86TargetMachine.h | 2 +- llvm/lib/Target/XCore/XCoreTargetMachine.cpp | 4 ++-- llvm/lib/Target/XCore/XCoreTargetMachine.h | 2 +- llvm/tools/gold/gold-plugin.cpp | 2 +- llvm/tools/llc/llc.cpp | 2 +- llvm/tools/llvm-reduce/ReducerWorkItem.cpp | 2 +- 65 files changed, 126 insertions(+), 138 deletions(-) diff --git a/lld/Common/TargetOptionsCommandFlags.cpp b/lld/Common/TargetOptionsCommandFlags.cpp index 26e0fe6..0efe679 100644 --- a/lld/Common/TargetOptionsCommandFlags.cpp +++ b/lld/Common/TargetOptionsCommandFlags.cpp @@ -16,7 +16,7 @@ llvm::TargetOptions lld::initTargetOptionsFromCodeGenFlags() { return llvm::codegen::InitTargetOptionsFromCodeGenFlags(llvm::Triple()); } -llvm::Optional lld::getRelocModelFromCMModel() { +std::optional lld::getRelocModelFromCMModel() { return llvm::codegen::getExplicitRelocModel(); } diff --git a/lld/include/lld/Common/TargetOptionsCommandFlags.h b/lld/include/lld/Common/TargetOptionsCommandFlags.h index 02c7d40..9bc22d4 100644 --- a/lld/include/lld/Common/TargetOptionsCommandFlags.h +++ b/lld/include/lld/Common/TargetOptionsCommandFlags.h @@ -13,14 +13,13 @@ #ifndef LLD_COMMON_TARGETOPTIONSCOMMANDFLAGS_H #define LLD_COMMON_TARGETOPTIONSCOMMANDFLAGS_H -#include "llvm/ADT/Optional.h" #include "llvm/Support/CodeGen.h" #include "llvm/Target/TargetOptions.h" #include namespace lld { llvm::TargetOptions initTargetOptionsFromCodeGenFlags(); -llvm::Optional getRelocModelFromCMModel(); +std::optional getRelocModelFromCMModel(); std::optional getCodeModelFromCMModel(); std::string getCPUStr(); std::vector getMAttrs(); diff --git a/llvm/include/llvm/CodeGen/CommandFlags.h b/llvm/include/llvm/CodeGen/CommandFlags.h index c592738..a4f1ab84 100644 --- a/llvm/include/llvm/CodeGen/CommandFlags.h +++ b/llvm/include/llvm/CodeGen/CommandFlags.h @@ -38,7 +38,7 @@ std::string getMCPU(); std::vector getMAttrs(); Reloc::Model getRelocModel(); -Optional getExplicitRelocModel(); +std::optional getExplicitRelocModel(); ThreadModel::Model getThreadModel(); @@ -47,7 +47,7 @@ std::optional getExplicitCodeModel(); llvm::ExceptionHandling getExceptionModel(); -Optional getExplicitFileType(); +std::optional getExplicitFileType(); CodeGenFileType getFileType(); @@ -99,10 +99,10 @@ bool getLowerGlobalDtorsViaCxaAtExit(); bool getRelaxELFRelocations(); bool getDataSections(); -Optional getExplicitDataSections(); +std::optional getExplicitDataSections(); bool getFunctionSections(); -Optional getExplicitFunctionSections(); +std::optional getExplicitFunctionSections(); bool getIgnoreXCOFFVisibility(); diff --git a/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h b/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h index e2c7bb7..d82431c 100644 --- a/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h +++ b/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h @@ -541,7 +541,7 @@ private: std::shared_ptr MemMgr; std::shared_ptr Resolver; TargetOptions Options; - Optional RelocModel; + std::optional RelocModel; std::optional CMModel; std::string MArch; std::string MCPU; diff --git a/llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h b/llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h index 0c44e46..91cd326 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h @@ -84,13 +84,13 @@ public: const std::string &getCPU() const { return CPU; } /// Set the relocation model. - JITTargetMachineBuilder &setRelocationModel(Optional RM) { + JITTargetMachineBuilder &setRelocationModel(std::optional RM) { this->RM = std::move(RM); return *this; } /// Get the relocation model. - const Optional &getRelocationModel() const { return RM; } + const std::optional &getRelocationModel() const { return RM; } /// Set the code model. JITTargetMachineBuilder &setCodeModel(std::optional CM) { @@ -151,7 +151,7 @@ private: std::string CPU; SubtargetFeatures Features; TargetOptions Options; - Optional RM; + std::optional RM; std::optional CM; CodeGenOpt::Level OptLevel = CodeGenOpt::Default; }; diff --git a/llvm/include/llvm/LTO/Config.h b/llvm/include/llvm/LTO/Config.h index a709ddb..7cf837a 100644 --- a/llvm/include/llvm/LTO/Config.h +++ b/llvm/include/llvm/LTO/Config.h @@ -52,7 +52,7 @@ struct Config { std::vector PassPlugins; /// For adding passes that run right before codegen. std::function PreCodeGenPassesHook; - Optional RelocModel = Reloc::PIC_; + std::optional RelocModel = Reloc::PIC_; std::optional CodeModel = std::nullopt; CodeGenOpt::Level CGOptLevel = CodeGenOpt::Default; CodeGenFileType CGFileType = CGFT_ObjectFile; diff --git a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h index 5f64ca4..2093eaa 100644 --- a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h +++ b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h @@ -89,7 +89,7 @@ struct LTOCodeGenerator { void setAsmUndefinedRefs(struct LTOModule *); void setTargetOptions(const TargetOptions &Options); void setDebugInfo(lto_debug_model); - void setCodePICModel(Optional Model) { + void setCodePICModel(std::optional Model) { Config.RelocModel = Model; } diff --git a/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h b/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h index ab40d88..2df5182 100644 --- a/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h +++ b/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h @@ -37,7 +37,7 @@ struct TargetMachineBuilder { std::string MCpu; std::string MAttr; TargetOptions Options; - Optional RelocModel; + std::optional RelocModel; CodeGenOpt::Level CGOptLevel = CodeGenOpt::Aggressive; std::unique_ptr create() const; @@ -211,7 +211,7 @@ public: void setFreestanding(bool Enabled) { Freestanding = Enabled; } /// CodeModel - void setCodePICModel(Optional Model) { + void setCodePICModel(std::optional Model) { TMBuilder.RelocModel = Model; } diff --git a/llvm/include/llvm/MC/TargetRegistry.h b/llvm/include/llvm/MC/TargetRegistry.h index 4c98cbc..e396596 100644 --- a/llvm/include/llvm/MC/TargetRegistry.h +++ b/llvm/include/llvm/MC/TargetRegistry.h @@ -167,7 +167,7 @@ public: StringRef Features); using TargetMachineCtorTy = TargetMachine *(*)(const Target &T, const Triple &TT, StringRef CPU, StringRef Features, - const TargetOptions &Options, Optional RM, + const TargetOptions &Options, std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); // If it weren't for layering issues (this header is in llvm/Support, but // depends on MC?) this should take the Streamer by value rather than rvalue @@ -479,12 +479,11 @@ public: /// feature set; it should always be provided. Generally this should be /// either the target triple from the module, or the target triple of the /// host if that does not exist. - TargetMachine * - createTargetMachine(StringRef TT, StringRef CPU, StringRef Features, - const TargetOptions &Options, Optional RM, - std::optional CM = std::nullopt, - CodeGenOpt::Level OL = CodeGenOpt::Default, - bool JIT = false) const { + TargetMachine *createTargetMachine( + StringRef TT, StringRef CPU, StringRef Features, + const TargetOptions &Options, std::optional RM, + std::optional CM = std::nullopt, + CodeGenOpt::Level OL = CodeGenOpt::Default, bool JIT = false) const { if (!TargetMachineCtorFn) return nullptr; return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM, @@ -1362,7 +1361,7 @@ private: static TargetMachine *Allocator(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) { return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT); diff --git a/llvm/lib/CodeGen/CommandFlags.cpp b/llvm/lib/CodeGen/CommandFlags.cpp index 28b518a..68041f9 100644 --- a/llvm/lib/CodeGen/CommandFlags.cpp +++ b/llvm/lib/CodeGen/CommandFlags.cpp @@ -41,18 +41,8 @@ using namespace llvm; return *NAME##View; \ } -#define CGOPT_EXP(TY, NAME) \ - CGOPT(TY, NAME) \ - Optional codegen::getExplicit##NAME() { \ - if (NAME##View->getNumOccurrences()) { \ - TY res = *NAME##View; \ - return res; \ - } \ - return None; \ - } - // Temporary macro for incremental transition to std::optional. -#define CGSTDOPT_EXP(TY, NAME) \ +#define CGOPT_EXP(TY, NAME) \ CGOPT(TY, NAME) \ std::optional codegen::getExplicit##NAME() { \ if (NAME##View->getNumOccurrences()) { \ @@ -67,7 +57,7 @@ CGOPT(std::string, MCPU) CGLIST(std::string, MAttrs) CGOPT_EXP(Reloc::Model, RelocModel) CGOPT(ThreadModel::Model, ThreadModel) -CGSTDOPT_EXP(CodeModel::Model, CodeModel) +CGOPT_EXP(CodeModel::Model, CodeModel) CGOPT(ExceptionHandling, ExceptionModel) CGOPT_EXP(CodeGenFileType, FileType) CGOPT(FramePointerKind, FramePointerUsage) diff --git a/llvm/lib/LTO/LTOBackend.cpp b/llvm/lib/LTO/LTOBackend.cpp index 9762cb4..7a5f3a9 100644 --- a/llvm/lib/LTO/LTOBackend.cpp +++ b/llvm/lib/LTO/LTOBackend.cpp @@ -208,7 +208,7 @@ createTargetMachine(const Config &Conf, const Target *TheTarget, Module &M) { for (const std::string &A : Conf.MAttrs) Features.AddFeature(A); - Optional RelocModel; + std::optional RelocModel; if (Conf.RelocModel) RelocModel = *Conf.RelocModel; else if (M.getModuleFlag("PIC Level")) diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 2890f8d..b2844c4 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -275,7 +275,7 @@ static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) { } static Reloc::Model getEffectiveRelocModel(const Triple &TT, - Optional RM) { + std::optional RM) { // AArch64 Darwin and Windows are always PIC. if (TT.isOSDarwin() || TT.isOSWindows()) return Reloc::PIC_; @@ -315,7 +315,7 @@ getEffectiveAArch64CodeModel(const Triple &TT, AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT, bool LittleEndian) @@ -454,7 +454,7 @@ void AArch64leTargetMachine::anchor() { } AArch64leTargetMachine::AArch64leTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, - const TargetOptions &Options, Optional RM, + const TargetOptions &Options, std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} @@ -462,7 +462,7 @@ void AArch64beTargetMachine::anchor() { } AArch64beTargetMachine::AArch64beTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, - const TargetOptions &Options, Optional RM, + const TargetOptions &Options, std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h index e778409..ae9d706 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h @@ -29,7 +29,7 @@ protected: public: AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian); @@ -75,7 +75,7 @@ class AArch64leTargetMachine : public AArch64TargetMachine { public: AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); }; @@ -88,7 +88,7 @@ class AArch64beTargetMachine : public AArch64TargetMachine { public: AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); }; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index d4dd07f..7a9d37c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -522,7 +522,7 @@ static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) { return "r600"; } -static Reloc::Model getEffectiveRelocModel(Optional RM) { +static Reloc::Model getEffectiveRelocModel(std::optional RM) { // The AMDGPU toolchain only supports generating shared objects, so we // must always use PIC. return Reloc::PIC_; @@ -531,7 +531,7 @@ static Reloc::Model getEffectiveRelocModel(Optional RM) { AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OptLevel) : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU), @@ -801,7 +801,7 @@ AMDGPUTargetMachine::getAddressSpaceForPseudoSourceKind(unsigned Kind) const { GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {} diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h index af6c0f8..3e95573 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -40,7 +40,7 @@ public: AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL); ~AMDGPUTargetMachine() override; @@ -78,7 +78,7 @@ private: public: GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp index d5aa340..4a7e85b 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp @@ -51,7 +51,7 @@ static MachineSchedRegistry R600SchedRegistry("r600", R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) { diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.h b/llvm/lib/Target/AMDGPU/R600TargetMachine.h index 2c1fb03..ef5cc32 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetMachine.h +++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.h @@ -32,7 +32,7 @@ private: public: R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp index 11e9231..b51e2246 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp +++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -21,7 +21,7 @@ using namespace llvm; -static Reloc::Model getRelocModel(Optional RM) { +static Reloc::Model getRelocModel(std::optional RM) { return RM.value_or(Reloc::Static); } @@ -29,7 +29,7 @@ static Reloc::Model getRelocModel(Optional RM) { ARCTargetMachine::ARCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.h b/llvm/lib/Target/ARC/ARCTargetMachine.h index 53a0a0f..bb1484b 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.h +++ b/llvm/lib/Target/ARC/ARCTargetMachine.h @@ -28,7 +28,7 @@ class ARCTargetMachine : public LLVMTargetMachine { public: ARCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); ~ARCTargetMachine() override; diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 4417b51..1510690 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -196,7 +196,7 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU, } static Reloc::Model getEffectiveRelocModel(const Triple &TT, - Optional RM) { + std::optional RM) { if (!RM) // Default relocation model on Darwin is PIC. return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static; @@ -217,7 +217,7 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT, ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool isLittle) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, @@ -317,7 +317,7 @@ ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const { ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} @@ -325,7 +325,7 @@ ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT, ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h index cf1112b..b3d533a 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.h +++ b/llvm/lib/Target/ARM/ARMTargetMachine.h @@ -42,7 +42,7 @@ protected: public: ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool isLittle); ~ARMBaseTargetMachine() override; @@ -88,7 +88,7 @@ class ARMLETargetMachine : public ARMBaseTargetMachine { public: ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); }; @@ -99,7 +99,7 @@ class ARMBETargetMachine : public ARMBaseTargetMachine { public: ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); }; diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp index b280964..6b15962 100644 --- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp +++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp @@ -39,14 +39,14 @@ static StringRef getCPU(StringRef CPU) { return CPU; } -static Reloc::Model getEffectiveRelocModel(Optional RM) { +static Reloc::Model getEffectiveRelocModel(std::optional RM) { return RM.value_or(Reloc::Static); } AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options, diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.h b/llvm/lib/Target/AVR/AVRTargetMachine.h index 9289106..5ba689d 100644 --- a/llvm/lib/Target/AVR/AVRTargetMachine.h +++ b/llvm/lib/Target/AVR/AVRTargetMachine.h @@ -31,7 +31,7 @@ class AVRTargetMachine : public LLVMTargetMachine { public: AVRTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index 9bd7871..e0b48f1 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -58,14 +58,14 @@ static std::string computeDataLayout(const Triple &TT) { return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"; } -static Reloc::Model getEffectiveRelocModel(Optional RM) { +static Reloc::Model getEffectiveRelocModel(std::optional RM) { return RM.value_or(Reloc::PIC_); } BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.h b/llvm/lib/Target/BPF/BPFTargetMachine.h index 90eb7ba..1f22fcc 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.h +++ b/llvm/lib/Target/BPF/BPFTargetMachine.h @@ -25,7 +25,7 @@ class BPFTargetMachine : public LLVMTargetMachine { public: BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp index 8586ab6..9d1fe09 100644 --- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp +++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp @@ -49,7 +49,7 @@ static std::string computeDataLayout(const Triple &TT) { CSKYTargetMachine::CSKYTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.h b/llvm/lib/Target/CSKY/CSKYTargetMachine.h index a69dc82..3896003 100644 --- a/llvm/lib/Target/CSKY/CSKYTargetMachine.h +++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.h @@ -27,7 +27,7 @@ class CSKYTargetMachine : public LLVMTargetMachine { public: CSKYTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp index 985f73e..c72af04 100644 --- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp +++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp @@ -83,7 +83,7 @@ public: DirectXTargetMachine::DirectXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.h b/llvm/lib/Target/DirectX/DirectXTargetMachine.h index 396d204..a6a1b3e 100644 --- a/llvm/lib/Target/DirectX/DirectXTargetMachine.h +++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.h @@ -24,7 +24,7 @@ class DirectXTargetMachine : public LLVMTargetMachine { public: DirectXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 92748418..15ade4c 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -193,7 +193,7 @@ namespace llvm { FunctionPass *createHexagonVExtract(); } // end namespace llvm; -static Reloc::Model getEffectiveRelocModel(Optional RM) { +static Reloc::Model getEffectiveRelocModel(std::optional RM) { return RM.value_or(Reloc::Static); } @@ -223,7 +223,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() { HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) // Specify the vector alignment explicitly. For v512x1, the calculated diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h index a39637b..07213cf 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h @@ -30,7 +30,7 @@ class HexagonTargetMachine : public LLVMTargetMachine { public: HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); ~HexagonTargetMachine() override; diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp index 8ccbf2a..5e42745 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -48,13 +48,13 @@ static std::string computeDataLayout() { "-S64"; // 64 bit natural stack alignment } -static Reloc::Model getEffectiveRelocModel(Optional RM) { +static Reloc::Model getEffectiveRelocModel(std::optional RM) { return RM.value_or(Reloc::PIC_); } LanaiTargetMachine::LanaiTargetMachine( const Target &T, const Triple &TT, StringRef Cpu, StringRef FeatureString, - const TargetOptions &Options, Optional RM, + const TargetOptions &Options, std::optional RM, std::optional CodeModel, CodeGenOpt::Level OptLevel, bool JIT) : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options, diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.h b/llvm/lib/Target/Lanai/LanaiTargetMachine.h index e2ddf09..35ffca7 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.h +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.h @@ -30,7 +30,7 @@ public: LanaiTargetMachine(const Target &TheTarget, const Triple &TargetTriple, StringRef Cpu, StringRef FeatureString, const TargetOptions &Options, - Optional RelocationModel, + std::optional RM, std::optional CodeModel, CodeGenOpt::Level OptLevel, bool JIT); diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp index 872e935..af785ce 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp @@ -40,13 +40,13 @@ static std::string computeDataLayout(const Triple &TT) { } static Reloc::Model getEffectiveRelocModel(const Triple &TT, - Optional RM) { + std::optional RM) { return RM.value_or(Reloc::Static); } LoongArchTargetMachine::LoongArchTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, - const TargetOptions &Options, Optional RM, + const TargetOptions &Options, std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h index 62be57d..5a32ccc 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h +++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h @@ -26,7 +26,7 @@ class LoongArchTargetMachine : public LLVMTargetMachine { public: LoongArchTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); ~LoongArchTargetMachine() override; diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp index 4e1d4a5..97b6d6a 100644 --- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp +++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp @@ -71,7 +71,7 @@ std::string computeDataLayout(const Triple &TT, StringRef CPU, } Reloc::Model getEffectiveRelocModel(const Triple &TT, - Optional RM) { + std::optional RM) { // If not defined we default to static if (!RM.has_value()) return Reloc::Static; @@ -95,7 +95,7 @@ CodeModel::Model getEffectiveCodeModel(std::optional CM, M68kTargetMachine::M68kTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.h b/llvm/lib/Target/M68k/M68kTargetMachine.h index 83572b6..ab41519 100644 --- a/llvm/lib/Target/M68k/M68kTargetMachine.h +++ b/llvm/lib/Target/M68k/M68kTargetMachine.h @@ -37,7 +37,7 @@ class M68kTargetMachine : public LLVMTargetMachine { public: M68kTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp index 7edd735..f5a4fbf 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -27,7 +27,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430Target() { RegisterTargetMachine X(getTheMSP430Target()); } -static Reloc::Model getEffectiveRelocModel(Optional RM) { +static Reloc::Model getEffectiveRelocModel(std::optional RM) { return RM.value_or(Reloc::Static); } @@ -39,7 +39,7 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU, MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.h b/llvm/lib/Target/MSP430/MSP430TargetMachine.h index 533186b..400a938 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.h +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.h @@ -30,7 +30,7 @@ class MSP430TargetMachine : public LLVMTargetMachine { public: MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); ~MSP430TargetMachine() override; diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index a2fd27e..390fb23 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -106,7 +106,7 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU, } static Reloc::Model getEffectiveRelocModel(bool JIT, - Optional RM) { + std::optional RM) { if (!RM || JIT) return Reloc::Static; return *RM; @@ -120,7 +120,7 @@ static Reloc::Model getEffectiveRelocModel(bool JIT, MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT, bool isLittle) @@ -149,7 +149,7 @@ void MipsebTargetMachine::anchor() {} MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} @@ -159,7 +159,7 @@ void MipselTargetMachine::anchor() {} MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h index 3492d0c..b4961ab 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.h +++ b/llvm/lib/Target/Mips/MipsTargetMachine.h @@ -40,7 +40,7 @@ class MipsTargetMachine : public LLVMTargetMachine { public: MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT, bool isLittle); ~MipsTargetMachine() override; @@ -85,7 +85,7 @@ class MipsebTargetMachine : public MipsTargetMachine { public: MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); }; @@ -98,7 +98,7 @@ class MipselTargetMachine : public MipsTargetMachine { public: MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); }; diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 48357bc..56c605d 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -112,7 +112,7 @@ static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) { NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool is64bit) // The pic relocation model is used regardless of what the client has @@ -139,7 +139,7 @@ void NVPTXTargetMachine32::anchor() {} NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} @@ -149,7 +149,7 @@ void NVPTXTargetMachine64::anchor() {} NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h index 4b0db64..2b6ce69 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -37,7 +37,7 @@ class NVPTXTargetMachine : public LLVMTargetMachine { public: NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OP, bool is64bit); ~NVPTXTargetMachine() override; @@ -81,7 +81,7 @@ class NVPTXTargetMachine32 : public NVPTXTargetMachine { public: NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); }; @@ -92,7 +92,7 @@ class NVPTXTargetMachine64 : public NVPTXTargetMachine { public: NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); }; diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index f0ae664..cfc2f4b 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -246,7 +246,7 @@ static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, } static Reloc::Model getEffectiveRelocModel(const Triple &TT, - Optional RM) { + std::optional RM) { assert((!TT.isOSAIX() || !RM || *RM == Reloc::PIC_) && "Invalid relocation model for AIX."); @@ -325,7 +325,7 @@ static ScheduleDAGInstrs *createPPCPostMachineScheduler( PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU, diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h index b9c56a8..9351d10 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h @@ -38,7 +38,7 @@ private: public: PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index fe65d43..dff8ccc 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -76,14 +76,14 @@ static StringRef computeDataLayout(const Triple &TT) { } static Reloc::Model getEffectiveRelocModel(const Triple &TT, - Optional RM) { + std::optional RM) { return RM.value_or(Reloc::Static); } RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h index bd32321..d3102f1 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h @@ -28,7 +28,7 @@ class RISCVTargetMachine : public LLVMTargetMachine { public: RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp index b3aa534..1f1aa17 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp @@ -53,7 +53,7 @@ static std::string computeDataLayout(const Triple &TT) { "v96:128-v192:256-v256:256-v512:512-v1024:1024"; } -static Reloc::Model getEffectiveRelocModel(Optional RM) { +static Reloc::Model getEffectiveRelocModel(std::optional RM) { if (!RM) return Reloc::PIC_; return *RM; @@ -65,7 +65,7 @@ SPIRVTargetObjectFile::~SPIRVTargetObjectFile() {} SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h index f424639..cb16d7a0 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h @@ -25,7 +25,7 @@ class SPIRVTargetMachine : public LLVMTargetMachine { public: SPIRVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index ed61f50..2912f96 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -55,7 +55,7 @@ static std::string computeDataLayout(const Triple &T, bool is64Bit) { return Ret; } -static Reloc::Model getEffectiveRelocModel(Optional RM) { +static Reloc::Model getEffectiveRelocModel(std::optional RM) { return RM.value_or(Reloc::Static); } @@ -91,7 +91,7 @@ getEffectiveSparcCodeModel(std::optional CM, Reloc::Model RM, SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT, bool is64bit) @@ -191,7 +191,7 @@ void SparcV8TargetMachine::anchor() { } SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} @@ -201,7 +201,7 @@ void SparcV9TargetMachine::anchor() { } SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} @@ -211,7 +211,7 @@ void SparcelTargetMachine::anchor() {} SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h index 3f66b47..ee2d3ad 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.h +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h @@ -29,7 +29,7 @@ class SparcTargetMachine : public LLVMTargetMachine { public: SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT, bool is64bit); ~SparcTargetMachine() override; @@ -52,7 +52,7 @@ class SparcV8TargetMachine : public SparcTargetMachine { public: SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); }; @@ -65,7 +65,7 @@ class SparcV9TargetMachine : public SparcTargetMachine { public: SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); }; @@ -76,7 +76,7 @@ class SparcelTargetMachine : public SparcTargetMachine { public: SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); }; diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp index 0ea6c6d..36b3d05 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -85,7 +85,7 @@ static std::unique_ptr createTLOF(const Triple &TT) { return std::make_unique(); } -static Reloc::Model getEffectiveRelocModel(Optional RM) { +static Reloc::Model getEffectiveRelocModel(std::optional RM) { // Static code is suitable for use in a dynamic executable; there is no // separate DynamicNoPIC model. if (!RM || *RM == Reloc::DynamicNoPIC) @@ -140,7 +140,7 @@ getEffectiveSystemZCodeModel(std::optional CM, SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine( diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h index d36aeb7..130c583 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h @@ -33,7 +33,7 @@ class SystemZTargetMachine : public LLVMTargetMachine { public: SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); ~SystemZTargetMachine() override; diff --git a/llvm/lib/Target/TargetMachineC.cpp b/llvm/lib/Target/TargetMachineC.cpp index b6d238e..534a391 100644 --- a/llvm/lib/Target/TargetMachineC.cpp +++ b/llvm/lib/Target/TargetMachineC.cpp @@ -100,7 +100,7 @@ LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU, const char *Features, LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, LLVMCodeModel CodeModel) { - Optional RM; + std::optional RM; switch (Reloc){ case LLVMRelocStatic: RM = Reloc::Static; diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp b/llvm/lib/Target/VE/VETargetMachine.cpp index d26210c..48337a6 100644 --- a/llvm/lib/Target/VE/VETargetMachine.cpp +++ b/llvm/lib/Target/VE/VETargetMachine.cpp @@ -61,7 +61,7 @@ static std::string computeDataLayout(const Triple &T) { return Ret; } -static Reloc::Model getEffectiveRelocModel(Optional RM) { +static Reloc::Model getEffectiveRelocModel(std::optional RM) { return RM.value_or(Reloc::Static); } @@ -80,7 +80,7 @@ static std::unique_ptr createTLOF() { VETargetMachine::VETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, diff --git a/llvm/lib/Target/VE/VETargetMachine.h b/llvm/lib/Target/VE/VETargetMachine.h index 7428760..bb27322 100644 --- a/llvm/lib/Target/VE/VETargetMachine.h +++ b/llvm/lib/Target/VE/VETargetMachine.h @@ -30,8 +30,9 @@ class VETargetMachine : public LLVMTargetMachine { public: VETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, std::optional CM, - CodeGenOpt::Level OL, bool JIT); + std::optional RM, + std::optional CM, CodeGenOpt::Level OL, + bool JIT); ~VETargetMachine() override; const VESubtarget *getSubtargetImpl() const { return &Subtarget; } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index 5fa11fa..ffc3de2 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -86,7 +86,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeWebAssemblyTarget() { // WebAssembly Lowering public interface. //===----------------------------------------------------------------------===// -static Reloc::Model getEffectiveRelocModel(Optional RM, +static Reloc::Model getEffectiveRelocModel(std::optional RM, const Triple &TT) { if (!RM) { // Default to static relocation model. This should always be more optimial @@ -109,7 +109,7 @@ static Reloc::Model getEffectiveRelocModel(Optional RM, /// WebAssemblyTargetMachine::WebAssemblyTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, - const TargetOptions &Options, Optional RM, + const TargetOptions &Options, std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine( T, diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h index 92f2f3b..a8c39bc 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h @@ -28,7 +28,7 @@ class WebAssemblyTargetMachine final : public LLVMTargetMachine { public: WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index ee33f48..d03a5c6 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -163,9 +163,8 @@ static std::string computeDataLayout(const Triple &TT) { return Ret; } -static Reloc::Model getEffectiveRelocModel(const Triple &TT, - bool JIT, - Optional RM) { +static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT, + std::optional RM) { bool is64Bit = TT.getArch() == Triple::x86_64; if (!RM) { // JIT codegen should use static relocations by default, since it's @@ -223,7 +222,7 @@ getEffectiveX86CodeModel(std::optional CM, bool JIT, X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine( diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index 62a8c83..66b0ad6 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -35,7 +35,7 @@ class X86TargetMachine final : public LLVMTargetMachine { public: X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); ~X86TargetMachine() override; diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp index f56529a..6741ad9 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -26,7 +26,7 @@ using namespace llvm; -static Reloc::Model getEffectiveRelocModel(Optional RM) { +static Reloc::Model getEffectiveRelocModel(std::optional RM) { return RM.value_or(Reloc::Static); } @@ -45,7 +45,7 @@ getEffectiveXCoreCodeModel(std::optional CM) { XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine( diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.h b/llvm/lib/Target/XCore/XCoreTargetMachine.h index e612795..567af01 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.h +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.h @@ -31,7 +31,7 @@ class XCoreTargetMachine : public LLVMTargetMachine { public: XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, + std::optional RM, std::optional CM, CodeGenOpt::Level OL, bool JIT); ~XCoreTargetMachine() override; diff --git a/llvm/tools/gold/gold-plugin.cpp b/llvm/tools/gold/gold-plugin.cpp index c103fc4..0b26d5d 100644 --- a/llvm/tools/gold/gold-plugin.cpp +++ b/llvm/tools/gold/gold-plugin.cpp @@ -121,7 +121,7 @@ static ld_plugin_set_extra_library_path set_extra_library_path = nullptr; static ld_plugin_get_view get_view = nullptr; static bool IsExecutable = false; static bool SplitSections = true; -static Optional RelocationModel = None; +static std::optional RelocationModel = None; static std::string output_name = ""; static std::list Modules; static DenseMap FDToLeaderHandle; diff --git a/llvm/tools/llc/llc.cpp b/llvm/tools/llc/llc.cpp index 941b5d8..1a041a5 100644 --- a/llvm/tools/llc/llc.cpp +++ b/llvm/tools/llc/llc.cpp @@ -520,7 +520,7 @@ static int compileModule(char **argv, LLVMContext &Context) { } }; - Optional RM = codegen::getExplicitRelocModel(); + std::optional RM = codegen::getExplicitRelocModel(); std::optional CM = codegen::getExplicitCodeModel(); const Target *TheTarget = nullptr; diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp index 1126fde..ea5284a 100644 --- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp +++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp @@ -426,7 +426,7 @@ parseReducerWorkItem(const char *ToolName, StringRef Filename, // Hopefully the MIR parsing doesn't depend on any options. TargetOptions Options; - Optional RM = codegen::getExplicitRelocModel(); + std::optional RM = codegen::getExplicitRelocModel(); std::string CPUStr = codegen::getCPUStr(); std::string FeaturesStr = codegen::getFeaturesStr(); TM = std::unique_ptr(TheTarget->createTargetMachine( -- 2.7.4