From baaeca7d1ac7cc0abd50ce265d41990281607b41 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 24 May 2022 15:09:00 +0800 Subject: [PATCH] radeonsi: implement nir_intrinsic_load_tess_rel_patch_id_amd for both tcs and tes MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit radv will lower this intrinsic before gets to llvm, so we just need to implement it in radeonsi. The tes version will be used in tess lower too. Reviewed-by: Marek Olšák Acked-by: Pierre-Eric Pelloux-Prayer Signed-off-by: Qiang Yu Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 5 +---- src/gallium/drivers/radeonsi/si_shader_internal.h | 1 + src/gallium/drivers/radeonsi/si_shader_llvm.c | 3 +++ src/gallium/drivers/radeonsi/si_shader_llvm_tess.c | 12 ++++++------ 4 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index deb7db0..920fd5a 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3631,6 +3631,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins case nir_intrinsic_load_tess_level_inner: case nir_intrinsic_load_tess_level_outer_default: case nir_intrinsic_load_tess_level_inner_default: + case nir_intrinsic_load_tess_rel_patch_id_amd: case nir_intrinsic_load_patch_vertices_in: case nir_intrinsic_load_sample_mask_in: case nir_intrinsic_load_ring_tess_factors_amd: @@ -4050,10 +4051,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins result = ac_build_gather_values(&ctx->ac, coord, 3); break; } - case nir_intrinsic_load_tess_rel_patch_id_amd: - assert(ctx->stage == MESA_SHADER_TESS_CTRL); - result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->tcs_rel_ids), 0, 8); - break; case nir_intrinsic_vote_all: { result = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0])); break; diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h index 8f41bd4..cbb4a51 100644 --- a/src/gallium/drivers/radeonsi/si_shader_internal.h +++ b/src/gallium/drivers/radeonsi/si_shader_internal.h @@ -242,6 +242,7 @@ void si_llvm_gs_build_end(struct si_shader_context *ctx); void si_llvm_init_gs_callbacks(struct si_shader_context *ctx); /* si_shader_llvm_tess.c */ +LLVMValueRef si_get_rel_patch_id(struct si_shader_context *ctx); LLVMValueRef si_get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx); LLVMValueRef si_get_num_tcs_out_vertices(struct si_shader_context *ctx); void si_llvm_preload_tess_rings(struct si_shader_context *ctx); diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c index 136a28d..8f3263a 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c @@ -794,6 +794,9 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin case nir_intrinsic_load_ring_tess_offchip_offset_amd: return ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); + case nir_intrinsic_load_tess_rel_patch_id_amd: + return si_get_rel_patch_id(ctx); + default: return NULL; } diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c index 49b2cc6..70ab6e3 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c @@ -26,7 +26,7 @@ #include "si_shader_internal.h" #include "sid.h" -static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx) +LLVMValueRef si_get_rel_patch_id(struct si_shader_context *ctx) { switch (ctx->stage) { case MESA_SHADER_TESS_CTRL: @@ -106,7 +106,7 @@ static LLVMValueRef get_tcs_out_patch0_patch_data_offset(struct si_shader_contex static LLVMValueRef get_tcs_in_current_patch_offset(struct si_shader_context *ctx) { LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx); - LLVMValueRef rel_patch_id = get_rel_patch_id(ctx); + LLVMValueRef rel_patch_id = si_get_rel_patch_id(ctx); return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, ""); } @@ -115,7 +115,7 @@ static LLVMValueRef get_tcs_out_current_patch_offset(struct si_shader_context *c { LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx); LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx); - LLVMValueRef rel_patch_id = get_rel_patch_id(ctx); + LLVMValueRef rel_patch_id = si_get_rel_patch_id(ctx); return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset); } @@ -124,7 +124,7 @@ static LLVMValueRef get_tcs_out_current_patch_data_offset(struct si_shader_conte { LLVMValueRef patch0_patch_data_offset = get_tcs_out_patch0_patch_data_offset(ctx); LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx); - LLVMValueRef rel_patch_id = get_rel_patch_id(ctx); + LLVMValueRef rel_patch_id = si_get_rel_patch_id(ctx); return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset); } @@ -258,7 +258,7 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(struct si_sh param_index = LLVMConstInt(ctx->ac.i32, param_index_base, 0); } - return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), vertex_index, param_index); + return get_tcs_tes_buffer_address(ctx, si_get_rel_patch_id(ctx), vertex_index, param_index); } static LLVMValueRef buffer_load(struct si_shader_context *ctx, LLVMTypeRef type, unsigned swizzle, @@ -711,7 +711,7 @@ void si_llvm_tcs_build_end(struct si_shader_context *ctx) LLVMBuilderRef builder = ctx->ac.builder; LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset; - rel_patch_id = get_rel_patch_id(ctx); + rel_patch_id = si_get_rel_patch_id(ctx); invocation_id = si_unpack_param(ctx, ctx->args.tcs_rel_ids, 8, 5); tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx); -- 2.7.4