From ba96796544f3bfc53a3269f0cf65651e349f8033 Mon Sep 17 00:00:00 2001 From: Devin Heitmueller Date: Sun, 13 Mar 2011 01:54:02 -0300 Subject: [PATCH] [media] drxd: provide ability to control rs byte Provide the ability for the board configuration to specify whether to insert the RS byte into the TS interconnect to the bridge, while not required for the ngene in fact is required for the em28xx. Signed-off-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb/frontends/drxd.h | 1 + drivers/media/dvb/frontends/drxd_hard.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h index 9b11dc8..81093b9 100644 --- a/drivers/media/dvb/frontends/drxd.h +++ b/drivers/media/dvb/frontends/drxd.h @@ -38,6 +38,7 @@ struct drxd_config #define DRXD_PLL_MT3X0823 2 u32 clock; + u8 insert_rs_byte; u8 demod_address; u8 demoda_address; diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c index c4835b3..994195f 100644 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -2449,7 +2449,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) state->tuner_mirrors=0; /* modify MPEG output attributes */ - state->insert_rs_byte = 0; + state->insert_rs_byte = state->config.insert_rs_byte; state->enable_parallel = (ulSerialMode != 1); /* Timing div, 250ns/Psys */ -- 2.7.4