From ba84e4cbec75db2cc71e9919c3aa43dd0fdf5389 Mon Sep 17 00:00:00 2001 From: bellard Date: Sat, 17 May 2008 19:24:07 +0000 Subject: [PATCH] converted sign extension ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4481 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-i386/op.c | 61 ------------------------------------------------- target-i386/translate.c | 46 +++++++++++++++++++++++++------------ 2 files changed, 31 insertions(+), 76 deletions(-) diff --git a/target-i386/op.c b/target-i386/op.c index 597b9f6..3f3e1f1 100644 --- a/target-i386/op.c +++ b/target-i386/op.c @@ -263,67 +263,6 @@ void OPPROTO op_cmpxchg8b(void) #endif -/* sign extend */ - -void OPPROTO op_movsbl_T0_T0(void) -{ - T0 = (int8_t)T0; -} - -void OPPROTO op_movzbl_T0_T0(void) -{ - T0 = (uint8_t)T0; -} - -void OPPROTO op_movswl_T0_T0(void) -{ - T0 = (int16_t)T0; -} - -void OPPROTO op_movzwl_T0_T0(void) -{ - T0 = (uint16_t)T0; -} - -void OPPROTO op_movswl_EAX_AX(void) -{ - EAX = (uint32_t)((int16_t)EAX); -} - -#ifdef TARGET_X86_64 -void OPPROTO op_movslq_T0_T0(void) -{ - T0 = (int32_t)T0; -} - -void OPPROTO op_movslq_RAX_EAX(void) -{ - EAX = (int32_t)EAX; -} -#endif - -void OPPROTO op_movsbw_AX_AL(void) -{ - EAX = (EAX & ~0xffff) | ((int8_t)EAX & 0xffff); -} - -void OPPROTO op_movslq_EDX_EAX(void) -{ - EDX = (uint32_t)((int32_t)EAX >> 31); -} - -void OPPROTO op_movswl_DX_AX(void) -{ - EDX = (EDX & ~0xffff) | (((int16_t)EAX >> 15) & 0xffff); -} - -#ifdef TARGET_X86_64 -void OPPROTO op_movsqo_RDX_RAX(void) -{ - EDX = (int64_t)EAX >> 63; -} -#endif - /* string ops helpers */ void OPPROTO op_addl_ESI_T0(void) diff --git a/target-i386/translate.c b/target-i386/translate.c index 4ce1038..dc7bb03 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4109,24 +4109,40 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x98: /* CWDE/CBW */ #ifdef TARGET_X86_64 if (dflag == 2) { - gen_op_movslq_RAX_EAX(); + gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); + tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); + gen_op_mov_reg_T0(OT_QUAD, R_EAX); } else #endif - if (dflag == 1) - gen_op_movswl_EAX_AX(); - else - gen_op_movsbw_AX_AL(); + if (dflag == 1) { + gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); + tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); + gen_op_mov_reg_T0(OT_LONG, R_EAX); + } else { + gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX); + tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); + gen_op_mov_reg_T0(OT_WORD, R_EAX); + } break; case 0x99: /* CDQ/CWD */ #ifdef TARGET_X86_64 if (dflag == 2) { - gen_op_movsqo_RDX_RAX(); + gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); + tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); + gen_op_mov_reg_T0(OT_QUAD, R_EDX); } else #endif - if (dflag == 1) - gen_op_movslq_EDX_EAX(); - else - gen_op_movswl_DX_AX(); + if (dflag == 1) { + gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); + tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); + tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); + gen_op_mov_reg_T0(OT_LONG, R_EDX); + } else { + gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); + tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); + tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); + gen_op_mov_reg_T0(OT_WORD, R_EDX); + } break; case 0x1af: /* imul Gv, Ev */ case 0x69: /* imul Gv, Ev, I */ @@ -4479,17 +4495,17 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_mov_TN_reg(ot, 0, rm); switch(ot | (b & 8)) { case OT_BYTE: - gen_op_movzbl_T0_T0(); + tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); break; case OT_BYTE | 8: - gen_op_movsbl_T0_T0(); + tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); break; case OT_WORD: - gen_op_movzwl_T0_T0(); + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); break; default: case OT_WORD | 8: - gen_op_movswl_T0_T0(); + tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); break; } gen_op_mov_reg_T0(d_ot, reg); @@ -6481,7 +6497,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_mov_TN_reg(OT_LONG, 0, rm); /* sign extend */ if (d_ot == OT_QUAD) - gen_op_movslq_T0_T0(); + tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); gen_op_mov_reg_T0(d_ot, reg); } else { gen_lea_modrm(s, modrm, ®_addr, &offset_addr); -- 2.7.4