From ba83052961209a065f7e907bb0e93ee7a4964ba9 Mon Sep 17 00:00:00 2001 From: Zhuo Wang Date: Mon, 26 Mar 2018 16:47:45 +0800 Subject: [PATCH] ethernet: add eye pattern and phy default value PD#163016: add eye pattern and modify internal phy status Change-Id: I18e0164646b17b86187fe1fe5c0189c9c2302130 Signed-off-by: Zhuo Wang --- drivers/amlogic/ethernet/phy/phy_debug.c | 32 +++++++++++++++++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c | 6 ++--- 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/amlogic/ethernet/phy/phy_debug.c b/drivers/amlogic/ethernet/phy/phy_debug.c index 63eaf0d..cbe9b5f 100644 --- a/drivers/amlogic/ethernet/phy/phy_debug.c +++ b/drivers/amlogic/ethernet/phy/phy_debug.c @@ -548,6 +548,27 @@ static void am_net_adc_show(void) } } +static void am_net_eye_pattern_on(void) +{ + unsigned int value; + + c_phy_dev->autoneg = AUTONEG_DISABLE; + phy_write(c_phy_dev, 0, 0x2100); + value = phy_read(c_phy_dev, 17); + pr_info("0x11 %x\n", value); + phy_write(c_phy_dev, 17, (value | 0x0004)); +} +static void am_net_eye_pattern_off(void) +{ + unsigned int value; + + c_phy_dev->autoneg = AUTONEG_ENABLE; + phy_write(c_phy_dev, 0, 0x1000); + value = phy_read(c_phy_dev, 17); + pr_info("0x11 %x\n", value); + phy_write(c_phy_dev, 17, (value & ~0x0004)); +} + static ssize_t eth_phyreg_func( struct class *class, struct class_attribute *attr, const char *buf, size_t count) @@ -611,6 +632,17 @@ static ssize_t eth_phyreg_func( am_close_tst_mode(); break; + case 'o': + case 'O': + if (argv[0][1] == 'n' || argv[0][1] == 'N') { + am_net_eye_pattern_on(); + break; + } + if (argv[0][1] == 'f' || argv[0][1] == 'F') { + am_net_eye_pattern_off(); + break; + } + break; default: goto end; } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c index c7a23a1..949425e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c @@ -223,9 +223,9 @@ static int dwmac_meson_cfg_ctrl(void __iomem *base_addr) /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/ writel(0x260, ETH_PHY_config_addr + ETH_PHY_CNTL2); - writel(0x74043, ETH_PHY_config_addr + ETH_PHY_CNTL1); - writel(0x34043, ETH_PHY_config_addr + ETH_PHY_CNTL1); - writel(0x74043, ETH_PHY_config_addr + ETH_PHY_CNTL1); + writel(0x54147, ETH_PHY_config_addr + ETH_PHY_CNTL1); + writel(0x14147, ETH_PHY_config_addr + ETH_PHY_CNTL1); + writel(0x54147, ETH_PHY_config_addr + ETH_PHY_CNTL1); return 0; } -- 2.7.4