From ba72bdef3250ce2ef602d7a07af6a5a6c5255fde Mon Sep 17 00:00:00 2001 From: Hsiangkai Wang Date: Thu, 8 Apr 2021 10:49:10 +0800 Subject: [PATCH] [RISCV] Add scalable offset under very large stack size. If the stack size is larger than 12 bits, we have to use a scratch register to store the stack size. Before we introduce the scalable stack offset, we could simplify %0 = ADDI %stack.0, 0 => %scratch = ... # sequence of instructions to move the offset into %%scratch %0 = ADD %fp, %scratch However, if the offset contains scalable part, we need to consider it. %0 = ADDI %stack.0, 0 => %scratch = ... # sequence of instructions to move the offset into %%scratch %scratch = ADD %fp, %scratch %scalable_offset = ... # sequence of instructions for vscaled-offset. %0 = ADD/SUB %scratch, %scalable_offset Differential Revision: https://reviews.llvm.org/D100035 --- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 9 ++++++++- llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir | 2 ++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 7428f10..e6a50c7 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -213,7 +213,7 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // Modify Offset and FrameReg appropriately Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); TII->movImm(MBB, II, DL, ScratchReg, Offset.getFixed()); - if (MI.getOpcode() == RISCV::ADDI) { + if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) { BuildMI(MBB, II, DL, TII->get(RISCV::ADD), MI.getOperand(0).getReg()) .addReg(FrameReg) .addReg(ScratchReg, RegState::Kill); @@ -258,6 +258,13 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue); // 2. Calculate address: FrameReg + result of multiply + if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) { + BuildMI(MBB, II, DL, TII->get(Opc), MI.getOperand(0).getReg()) + .addReg(FrameReg, getKillRegState(FrameRegIsKill)) + .addReg(FactorRegister, RegState::Kill); + MI.eraseFromParent(); + return; + } Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); BuildMI(MBB, II, DL, TII->get(Opc), VL) .addReg(FrameReg, getKillRegState(FrameRegIsKill)) diff --git a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir index 7b017e7..efb6656 100644 --- a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir +++ b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir @@ -43,6 +43,8 @@ body: | ; CHECK: $x10 = LUI 1048575 ; CHECK: $x10 = ADDIW killed $x10, 1824 ; CHECK: $x10 = ADD $x8, killed $x10 + ; CHECK: $x11 = PseudoReadVLENB + ; CHECK: $x10 = SUB killed $x10, killed $x11 ; CHECK: VS1R_V killed renamable $v25, killed renamable $x10 ; CHECK: $x10 = PseudoReadVLENB ; CHECK: $x2 = ADD $x2, killed $x10 -- 2.7.4