From ba1047bbf017ba05ecd72011e2173f4073794d60 Mon Sep 17 00:00:00 2001 From: Shunzhou Jiang Date: Fri, 1 Feb 2019 09:45:46 +0800 Subject: [PATCH] clk: g12a/g12b: update pcie clk parameter for jitter [1/1] PD#SWPL-4745 Problem: update pcie parameter for jitter Solution: clear pcie clk parameter Verify: test pass on g12a skt/w400 Change-Id: I354d643c412c37fb6c99fc49ac5bd70ab12be008 Signed-off-by: Shunzhou Jiang --- drivers/amlogic/clk/g12a/g12a_clk-pll.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/amlogic/clk/g12a/g12a_clk-pll.c b/drivers/amlogic/clk/g12a/g12a_clk-pll.c index 194ba7d..0f67ff3 100644 --- a/drivers/amlogic/clk/g12a/g12a_clk-pll.c +++ b/drivers/amlogic/clk/g12a/g12a_clk-pll.c @@ -51,10 +51,10 @@ /* G12A */ //#define G12A_PCIE_PLL_CNTL 0x400106c8 -#define G12A_PCIE_PLL_CNTL0_0 0x20090496 -#define G12A_PCIE_PLL_CNTL0_1 0x30090496 -#define G12A_PCIE_PLL_CNTL0_2 0x34090496 -#define G12A_PCIE_PLL_CNTL0_3 0x14090496 +#define G12A_PCIE_PLL_CNTL0_0 0x28060464 +#define G12A_PCIE_PLL_CNTL0_1 0x38060464 +#define G12A_PCIE_PLL_CNTL0_2 0x3c060464 +#define G12A_PCIE_PLL_CNTL0_3 0x1c060464 #define G12A_PCIE_PLL_CNTL1 0x00000000 #define G12A_PCIE_PLL_CNTL2 0x00001100 #define G12A_PCIE_PLL_CNTL2_ 0x00001000 @@ -64,10 +64,10 @@ #define G12A_PCIE_PLL_CNTL5 0x68000048 #define G12A_PCIE_PLL_CNTL5_ 0x68000068 -#define G12B_PCIE_PLL_CNTL0_0 0x200c04c8 -#define G12B_PCIE_PLL_CNTL0_1 0x300c04c8 -#define G12B_PCIE_PLL_CNTL0_2 0x340c04c8 -#define G12B_PCIE_PLL_CNTL0_3 0x140c04c8 +#define G12B_PCIE_PLL_CNTL0_0 0x28060464 +#define G12B_PCIE_PLL_CNTL0_1 0x38060464 +#define G12B_PCIE_PLL_CNTL0_2 0x3c060464 +#define G12B_PCIE_PLL_CNTL0_3 0x1c060464 #define G12B_PCIE_PLL_CNTL1 0x00000000 #define G12B_PCIE_PLL_CNTL2 0x00001100 #define G12B_PCIE_PLL_CNTL2_ 0x00001000 -- 2.7.4