From ba089425fd0044d910a58bbfb4b9952b1d2e84e5 Mon Sep 17 00:00:00 2001 From: Long Yu Date: Mon, 15 Apr 2019 16:40:25 +0800 Subject: [PATCH] emmc: Clear the value of txdelay in legacy mode on the resume process [1/1] PD#SWPL-7181 Problem: switch to high-speed from hs200 failed for resume process. Solution: set tx_delay as 0 for legacy mode. clear cfg_cmd_setup Verify: verify by TL1 Change-Id: I5dbb1bbc391da864464bf137837a2b0f54ccda42 Signed-off-by: Long Yu --- arch/arm/boot/dts/amlogic/mesontl1.dtsi | 2 +- arch/arm64/boot/dts/amlogic/mesontl1.dtsi | 2 +- drivers/amlogic/mmc/aml_sd_emmc_v3.c | 5 +++++ 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/amlogic/mesontl1.dtsi b/arch/arm/boot/dts/amlogic/mesontl1.dtsi index 92f4b6b..b64e30a 100644 --- a/arch/arm/boot/dts/amlogic/mesontl1.dtsi +++ b/arch/arm/boot/dts/amlogic/mesontl1.dtsi @@ -1160,7 +1160,7 @@ tx_delay = <0>; max_req_size = <0x20000>; /**128KB*/ gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; - hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; card_type = <1>; /* 1:mmc card(include eMMC), * 2:sd card(include tSD) diff --git a/arch/arm64/boot/dts/amlogic/mesontl1.dtsi b/arch/arm64/boot/dts/amlogic/mesontl1.dtsi index 0402bec3..b8cf37f 100644 --- a/arch/arm64/boot/dts/amlogic/mesontl1.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesontl1.dtsi @@ -1141,7 +1141,7 @@ tx_delay = <0>; max_req_size = <0x20000>; /**128KB*/ gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; - hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; card_type = <1>; /* 1:mmc card(include eMMC), * 2:sd card(include tSD) diff --git a/drivers/amlogic/mmc/aml_sd_emmc_v3.c b/drivers/amlogic/mmc/aml_sd_emmc_v3.c index 4f28b8cb..52922d0 100644 --- a/drivers/amlogic/mmc/aml_sd_emmc_v3.c +++ b/drivers/amlogic/mmc/aml_sd_emmc_v3.c @@ -396,6 +396,11 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata, clkc->tx_phase = para->sdr104.tx_phase; } else { ctrl->ddr = 0; + clkc->tx_delay = 0; + clkc->core_phase = para->init.core_phase; + clkc->tx_phase = para->init.tx_phase; + irq_en &= ~(1<<17); + writel(irq_en, host->base + SD_EMMC_IRQ_EN); /* timing == MMC_TIMING_LEGACY */ if (pdata->calc_f) { clkc->core_phase = para->calc.core_phase; -- 2.7.4