From b9cb0a44c1e940f4c577b67e504c3a8aacae6a3e Mon Sep 17 00:00:00 2001 From: Tejas Belagod Date: Thu, 19 Dec 2013 15:00:53 +0000 Subject: [PATCH] Implement support for AArch64 Crypto SHA256. gcc/ * config/aarch64/aarch64-simd-builtins.def: Update builtins table. * config/aarch64/aarch64-simd.md (aarch64_crypto_sha256hv4si, aarch64_crypto_sha256su0v4si, aarch64_crypto_sha256su1v4si): New. * config/aarch64/arm_neon.h (vsha256hq_u32, vsha256h2q_u32, vsha256su0q_u32, vsha256su1q_u32): New. * config/aarch64/iterators.md (UNSPEC_SHA256H<2>, UNSPEC_SHA256SU<01>): New. (CRYPTO_SHA256): New int iterator. (sha256_op): New int attribute. testsuite/ * gcc.target/aarch64/sha256_1.c: New. From-SVN: r206119 --- gcc/ChangeLog | 12 +++++++++ gcc/config/aarch64/aarch64-simd-builtins.def | 6 +++++ gcc/config/aarch64/aarch64-simd.md | 34 +++++++++++++++++++++++ gcc/config/aarch64/arm_neon.h | 24 +++++++++++++++++ gcc/config/aarch64/iterators.md | 8 ++++++ gcc/testsuite/ChangeLog | 4 +++ gcc/testsuite/gcc.target/aarch64/sha256_1.c | 40 ++++++++++++++++++++++++++++ 7 files changed, 128 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/sha256_1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1886afb..1c4a9fc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,18 @@ 2013-12-19 Tejas Belagod * config/aarch64/aarch64-simd-builtins.def: Update builtins table. + * config/aarch64/aarch64-simd.md (aarch64_crypto_sha256hv4si, + aarch64_crypto_sha256su0v4si, aarch64_crypto_sha256su1v4si): New. + * config/aarch64/arm_neon.h (vsha256hq_u32, vsha256h2q_u32, + vsha256su0q_u32, vsha256su1q_u32): New. + * config/aarch64/iterators.md (UNSPEC_SHA256H<2>, UNSPEC_SHA256SU<01>): + New. + (CRYPTO_SHA256): New int iterator. + (sha256_op): New int attribute. + +2013-12-19 Tejas Belagod + + * config/aarch64/aarch64-simd-builtins.def: Update builtins table. * config/aarch64/aarch64-builtins.c (aarch64_types_ternopu_qualifiers, TYPES_TERNOPU): New. * config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hsi, diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 7f90c82..c7e1120 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -380,3 +380,9 @@ VAR1 (TERNOPU, crypto_sha1m, 0, v4si) VAR1 (TERNOPU, crypto_sha1p, 0, v4si) VAR1 (TERNOPU, crypto_sha1su0, 0, v4si) + + /* Implemented by aarch64_crypto_sha256. */ + VAR1 (TERNOPU, crypto_sha256h, 0, v4si) + VAR1 (TERNOPU, crypto_sha256h2, 0, v4si) + VAR1 (BINOPU, crypto_sha256su0, 0, v4si) + VAR1 (TERNOPU, crypto_sha256su1, 0, v4si) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5b454ca..874d532 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4139,3 +4139,37 @@ "sha1su0\\t%0.4s, %2.4s, %3.4s" [(set_attr "type" "crypto_sha1_xor")] ) + +;; sha256 + +(define_insn "aarch64_crypto_sha256hv4si" + [(set (match_operand:V4SI 0 "register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") + (match_operand:V4SI 2 "register_operand" "w") + (match_operand:V4SI 3 "register_operand" "w")] + CRYPTO_SHA256))] + "TARGET_SIMD && TARGET_CRYPTO" + "sha256h\\t%q0, %q2, %3.4s" + [(set_attr "type" "crypto_sha256_slow")] +) + +(define_insn "aarch64_crypto_sha256su0v4si" + [(set (match_operand:V4SI 0 "register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") + (match_operand:V4SI 2 "register_operand" "w")] + UNSPEC_SHA256SU0))] + "TARGET_SIMD &&TARGET_CRYPTO" + "sha256su0\\t%0.4s, %2.4s" + [(set_attr "type" "crypto_sha256_fast")] +) + +(define_insn "aarch64_crypto_sha256su1v4si" + [(set (match_operand:V4SI 0 "register_operand" "=w") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") + (match_operand:V4SI 2 "register_operand" "w") + (match_operand:V4SI 3 "register_operand" "w")] + UNSPEC_SHA256SU1))] + "TARGET_SIMD &&TARGET_CRYPTO" + "sha256su1\\t%0.4s, %2.4s, %3.4s" + [(set_attr "type" "crypto_sha256_slow")] +) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 5a5691d..709c6a1 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -22990,6 +22990,30 @@ vsha1su1q_u32 (uint32x4_t tw0_3, uint32x4_t w12_15) return __builtin_aarch64_crypto_sha1su1v4si_uuu (tw0_3, w12_15); } +static __inline uint32x4_t +vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk) +{ + return __builtin_aarch64_crypto_sha256hv4si_uuuu (hash_abcd, hash_efgh, wk); +} + +static __inline uint32x4_t +vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk) +{ + return __builtin_aarch64_crypto_sha256h2v4si_uuuu (hash_efgh, hash_abcd, wk); +} + +static __inline uint32x4_t +vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7) +{ + return __builtin_aarch64_crypto_sha256su0v4si_uuu (w0_3, w4_7); +} + +static __inline uint32x4_t +vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15) +{ + return __builtin_aarch64_crypto_sha256su1v4si_uuuu (tw0_3, w8_11, w12_15); +} + #endif /* vshl */ diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 12de4ac..88edddd 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -277,6 +277,10 @@ UNSPEC_SHA1H ; Used in aarch64-simd.md. UNSPEC_SHA1SU0 ; Used in aarch64-simd.md. UNSPEC_SHA1SU1 ; Used in aarch64-simd.md. + UNSPEC_SHA256H ; Used in aarch64-simd.md. + UNSPEC_SHA256H2 ; Used in aarch64-simd.md. + UNSPEC_SHA256SU0 ; Used in aarch64-simd.md. + UNSPEC_SHA256SU1 ; Used in aarch64-simd.md. ]) ;; ------------------------------------------------------------------- @@ -863,6 +867,8 @@ (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) +(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2]) + ;; ------------------------------------------------------------------- ;; Int Iterators Attributes. ;; ------------------------------------------------------------------- @@ -985,3 +991,5 @@ (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p") (UNSPEC_SHA1M "m")]) + +(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 849d1f7..2ee577e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2013-12-19 Tejas Belagod + * gcc.target/aarch64/sha256_1.c: New. + +2013-12-19 Tejas Belagod + * gcc.target/aarch64/sha1_1.c: New. 2013-12-19 Tejas Belagod diff --git a/gcc/testsuite/gcc.target/aarch64/sha256_1.c b/gcc/testsuite/gcc.target/aarch64/sha256_1.c new file mode 100644 index 0000000..569817e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sha256_1.c @@ -0,0 +1,40 @@ + +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+crypto" } */ + +#include "arm_neon.h" + +uint32x4_t +test_vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk) +{ + return vsha256hq_u32 (hash_abcd, hash_efgh, wk); +} + +/* { dg-final { scan-assembler-times "sha256h\\tq" 1 } } */ + +uint32x4_t +test_vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk) +{ + return vsha256h2q_u32 (hash_efgh, hash_abcd, wk); +} + +/* { dg-final { scan-assembler-times "sha256h2\\tq" 1 } } */ + +uint32x4_t +test_vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7) +{ + return vsha256su0q_u32 (w0_3, w4_7); +} + +/* { dg-final { scan-assembler-times "sha256su0\\tv" 1 } } */ + +uint32x4_t +test_vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15) +{ + return vsha256su1q_u32 (tw0_3, w8_11, w12_15); +} + +/* { dg-final { scan-assembler-times "sha256su1\\tv" 1 } } */ + + +/* { dg-final { cleanup-saved-temps } } */ -- 2.7.4