From b9350895769de897280429e65c4840e8aeadfc54 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Nov 2014 18:18:28 +0000 Subject: [PATCH] R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies This fixes moving boolean constants into registers before operating on them. They get permuted and shrunk down to e32 anyway later. This is a temporary fix until the patch that removes these pseudos is committed. llvm-svn: 222844 --- llvm/lib/Target/R600/SILowerI1Copies.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/R600/SILowerI1Copies.cpp b/llvm/lib/Target/R600/SILowerI1Copies.cpp index 65b892c..226a672 100644 --- a/llvm/lib/Target/R600/SILowerI1Copies.cpp +++ b/llvm/lib/Target/R600/SILowerI1Copies.cpp @@ -93,19 +93,19 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) { if (MI.getOpcode() == AMDGPU::V_AND_I1) { I1Defs.push_back(MI.getOperand(0).getReg()); - MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32)); + MI.setDesc(TII->get(AMDGPU::V_AND_B32_e64)); continue; } if (MI.getOpcode() == AMDGPU::V_OR_I1) { I1Defs.push_back(MI.getOperand(0).getReg()); - MI.setDesc(TII->get(AMDGPU::V_OR_B32_e32)); + MI.setDesc(TII->get(AMDGPU::V_OR_B32_e64)); continue; } if (MI.getOpcode() == AMDGPU::V_XOR_I1) { I1Defs.push_back(MI.getOperand(0).getReg()); - MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e32)); + MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e64)); continue; } -- 2.7.4