From b934160aaa36be42d5b868704157f30339e7d855 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Thu, 7 Jan 2021 20:29:35 -0800 Subject: [PATCH] [Target] Use llvm::find_if (NFC) --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 16 +++++++--------- .../Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 9 ++++----- llvm/lib/Target/AMDGPU/GCNRegPressure.cpp | 5 ++--- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 9 ++++----- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 7 +++---- llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp | 14 ++++++++------ llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp | 4 ++-- llvm/lib/Target/X86/X86InstructionSelector.cpp | 7 +++---- 8 files changed, 33 insertions(+), 38 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 40435c1..fdf3acf 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -5425,10 +5425,10 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, // take care of putting the two halves in the right place but we have to // combine them. SDValue &Bits = - std::find_if(RegsToPass.begin(), RegsToPass.end(), - [=](const std::pair &Elt) { - return Elt.first == VA.getLocReg(); - }) + llvm::find_if(RegsToPass, + [=](const std::pair &Elt) { + return Elt.first == VA.getLocReg(); + }) ->second; Bits = DAG.getNode(ISD::OR, DL, Bits.getValueType(), Bits, Arg); // Call site info is used for function's parameter entry value @@ -5709,11 +5709,9 @@ AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, if (RegsUsed.count(VA.getLocReg())) { SDValue &Bits = - std::find_if(RetVals.begin(), RetVals.end(), - [=](const std::pair &Elt) { - return Elt.first == VA.getLocReg(); - }) - ->second; + llvm::find_if(RetVals, [=](const std::pair &Elt) { + return Elt.first == VA.getLocReg(); + })->second; Bits = DAG.getNode(ISD::OR, DL, Bits.getValueType(), Bits, Arg); } else { RetVals.emplace_back(VA.getLocReg(), Arg); diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 4a60fc7..7f68174 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -1578,11 +1578,10 @@ bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, if (!Symbols) return false; - auto Result = std::find_if(Symbols->begin(), Symbols->end(), - [Value](const SymbolInfoTy& Val) { - return Val.Addr == static_cast(Value) - && Val.Type == ELF::STT_NOTYPE; - }); + auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { + return Val.Addr == static_cast(Value) && + Val.Type == ELF::STT_NOTYPE; + }); if (Result != Symbols->end()) { auto *Sym = Ctx.getOrCreateSymbol(Result->Name); const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp index 7f66b41..7bac444 100644 --- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp +++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp @@ -224,9 +224,8 @@ collectVirtualRegUses(const MachineInstr &MI, const LiveIntervals &LIS, auto const UsedMask = getUsedRegMask(MO, MRI, LIS); auto Reg = MO.getReg(); - auto I = std::find_if(Res.begin(), Res.end(), [Reg](const RegisterMaskPair &RM) { - return RM.RegUnit == Reg; - }); + auto I = llvm::find_if( + Res, [Reg](const RegisterMaskPair &RM) { return RM.RegUnit == Reg; }); if (I != Res.end()) I->LaneMask |= UsedMask; else diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index de8ec4f..80fcb09 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -264,11 +264,10 @@ static bool lowerShiftReservedVGPR(MachineFunction &MF, // Find saved info about the pre-reserved register. const auto *ReservedVGPRInfoItr = - std::find_if(FuncInfo->getSGPRSpillVGPRs().begin(), - FuncInfo->getSGPRSpillVGPRs().end(), - [PreReservedVGPR](const auto &SpillRegInfo) { - return SpillRegInfo.VGPR == PreReservedVGPR; - }); + llvm::find_if(FuncInfo->getSGPRSpillVGPRs(), + [PreReservedVGPR](const auto &SpillRegInfo) { + return SpillRegInfo.VGPR == PreReservedVGPR; + }); assert(ReservedVGPRInfoItr != FuncInfo->getSGPRSpillVGPRs().end()); auto Index = diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 05f0499..3f9f902 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -6240,10 +6240,9 @@ bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { StringRef IDVal = Parser.getTok().getIdentifier(); const auto &Prefix = - std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries), - [&IDVal](const PrefixEntry &PE) { - return PE.Spelling == IDVal; - }); + llvm::find_if(PrefixEntries, [&IDVal](const PrefixEntry &PE) { + return PE.Spelling == IDVal; + }); if (Prefix == std::end(PrefixEntries)) { Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); return true; diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp index 0a53e53..9eff554 100644 --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp @@ -189,9 +189,10 @@ void AVRMCExpr::visitUsedExpr(MCStreamer &Streamer) const { } const char *AVRMCExpr::getName() const { - const auto &Modifier = std::find_if( - std::begin(ModifierNames), std::end(ModifierNames), - [this](ModifierEntry const &Mod) { return Mod.VariantKind == Kind; }); + const auto &Modifier = + llvm::find_if(ModifierNames, [this](ModifierEntry const &Mod) { + return Mod.VariantKind == Kind; + }); if (Modifier != std::end(ModifierNames)) { return Modifier->Spelling; @@ -200,9 +201,10 @@ const char *AVRMCExpr::getName() const { } AVRMCExpr::VariantKind AVRMCExpr::getKindByName(StringRef Name) { - const auto &Modifier = std::find_if( - std::begin(ModifierNames), std::end(ModifierNames), - [&Name](ModifierEntry const &Mod) { return Mod.Spelling == Name; }); + const auto &Modifier = + llvm::find_if(ModifierNames, [&Name](ModifierEntry const &Mod) { + return Mod.Spelling == Name; + }); if (Modifier != std::end(ModifierNames)) { return Modifier->VariantKind; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index 5c16f2b..a0763d6 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -1629,8 +1629,8 @@ SDValue WebAssemblyTargetLowering::LowerBUILD_VECTOR(SDValue Op, SmallVector SwizzleCounts; auto AddCount = [](auto &Counts, const auto &Val) { - auto CountIt = std::find_if(Counts.begin(), Counts.end(), - [&Val](auto E) { return E.first == Val; }); + auto CountIt = + llvm::find_if(Counts, [&Val](auto E) { return E.first == Val; }); if (CountIt == Counts.end()) { Counts.emplace_back(Val, 1); } else { diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp index 630df27..ff53171 100644 --- a/llvm/lib/Target/X86/X86InstructionSelector.cpp +++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp @@ -1559,10 +1559,9 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I, }}, // i64 }; - auto OpEntryIt = std::find_if(std::begin(OpTable), std::end(OpTable), - [RegTy](const DivRemEntry &El) { - return El.SizeInBits == RegTy.getSizeInBits(); - }); + auto OpEntryIt = llvm::find_if(OpTable, [RegTy](const DivRemEntry &El) { + return El.SizeInBits == RegTy.getSizeInBits(); + }); if (OpEntryIt == std::end(OpTable)) return false; -- 2.7.4