From b9245f14b799855a7b81010793ec5368e65d0f0f Mon Sep 17 00:00:00 2001 From: David Tenty Date: Tue, 7 Apr 2020 09:57:56 -0400 Subject: [PATCH] [NFC][PowerPC] Cleanup 64-bit and Darwin CalleeSavedRegs Summary: - Remove the no longer used Darwin CalleeSavedRegs - Combine the SVR464 callee saved regs and AIX64 since the two are (and should be) identical into PPC64 - Update tests for 64-bit CSR change Reviewers: sfertile, ZarkoCA, cebowleratibm, jasonliu, #powerpc Reviewed By: sfertile Subscribers: wuzish, nemanjai, hiraditya, kbarton, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77235 --- llvm/lib/Target/PowerPC/PPCCallingConv.td | 42 +++++---------------- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 21 +++++------ ...sableHoistingDueToBlockHotnessNoProfileData.mir | 2 +- ...DisableHoistingDueToBlockHotnessProfileData.mir | 2 +- llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir | 2 +- llvm/test/CodeGen/PowerPC/aix-cc-abi.ll | 44 +++++++++++----------- llvm/test/CodeGen/PowerPC/aix-cc-byval.ll | 22 +++++------ llvm/test/CodeGen/PowerPC/aix-indirect-call.ll | 4 +- llvm/test/CodeGen/PowerPC/aix-sret-param.ll | 4 +- llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll | 2 +- llvm/test/CodeGen/PowerPC/block-placement-1.mir | 20 +++++----- llvm/test/CodeGen/PowerPC/licm-tocReg.ll | 2 +- llvm/test/CodeGen/PowerPC/machine-backward-cp.mir | 4 +- llvm/test/CodeGen/PowerPC/setcr_bc.mir | 6 +-- llvm/test/CodeGen/PowerPC/setcr_bc2.mir | 6 +-- llvm/test/CodeGen/PowerPC/setcr_bc3.mir | 6 +-- llvm/test/CodeGen/PowerPC/test_call_aix.ll | 4 +- 17 files changed, 84 insertions(+), 109 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td index 369b9ce..d488213 100644 --- a/llvm/lib/Target/PowerPC/PPCCallingConv.td +++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td @@ -283,15 +283,6 @@ def CC_PPC32_SVR4_ByVal : CallingConv<[ def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27, V28, V29, V30, V31)>; -def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20, - R21, R22, R23, R24, R25, R26, R27, R28, - R29, R30, R31, F14, F15, F16, F17, F18, - F19, F20, F21, F22, F23, F24, F25, F26, - F27, F28, F29, F30, F31, CR2, CR3, CR4 - )>; - -def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>; - // SPE does not use FPRs, so break out the common register set as base. def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, @@ -316,45 +307,30 @@ def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20, F27, F28, F29, F30, F31, CR2, CR3, CR4 )>; -def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20, - X21, X22, X23, X24, X25, X26, X27, X28, - X29, X30, X31, F14, F15, F16, F17, F18, - F19, F20, F21, F22, F23, F24, F25, F26, - F27, F28, F29, F30, F31, CR2, CR3, CR4 - )>; - -def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>; - -def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, +// Common CalleeSavedRegs for SVR4 and AIX. +def CSR_PPC64 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31, CR2, CR3, CR4 )>; -def CSR_AIX64 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, - X21, X22, X23, X24, X25, X26, X27, X28, - X29, X30, X31, F14, F15, F16, F17, F18, - F19, F20, F21, F22, F23, F24, F25, F26, - F27, F28, F29, F30, F31, CR2, CR3, CR4 - )>; - // CSRs that are handled by prologue, epilogue. def CSR_SRV464_TLS_PE : CalleeSavedRegs<(add)>; -def CSR_SVR464_ViaCopy : CalleeSavedRegs<(add CSR_SVR464)>; +def CSR_SVR464_ViaCopy : CalleeSavedRegs<(add CSR_PPC64)>; -def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>; +def CSR_PPC64_Altivec : CalleeSavedRegs<(add CSR_PPC64, CSR_Altivec)>; -def CSR_SVR464_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_Altivec)>; +def CSR_SVR464_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_PPC64_Altivec)>; -def CSR_SVR464_R2 : CalleeSavedRegs<(add CSR_SVR464, X2)>; +def CSR_PPC64_R2 : CalleeSavedRegs<(add CSR_PPC64, X2)>; -def CSR_SVR464_R2_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_R2)>; +def CSR_SVR464_R2_ViaCopy : CalleeSavedRegs<(add CSR_PPC64_R2)>; -def CSR_SVR464_R2_Altivec : CalleeSavedRegs<(add CSR_SVR464_Altivec, X2)>; +def CSR_PPC64_R2_Altivec : CalleeSavedRegs<(add CSR_PPC64_Altivec, X2)>; -def CSR_SVR464_R2_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_R2_Altivec)>; +def CSR_SVR464_R2_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_PPC64_R2_Altivec)>; def CSR_NoRegs : CalleeSavedRegs<(add)>; diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index 24ad0f8..60153e1 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -174,10 +174,9 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { // Standard calling convention CSRs. if (TM.isPPC64()) { if (Subtarget.hasAltivec()) - return SaveR2 ? CSR_SVR464_R2_Altivec_SaveList - : CSR_SVR464_Altivec_SaveList; - return SaveR2 ? CSR_SVR464_R2_SaveList - : CSR_SVR464_SaveList; + return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList + : CSR_PPC64_Altivec_SaveList; + return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList; } // 32-bit targets. if (Subtarget.hasAltivec()) @@ -224,7 +223,7 @@ PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, if (Subtarget.isAIXABI()) { assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet."); - return TM.isPPC64() ? CSR_AIX64_RegMask : CSR_AIX32_RegMask; + return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask; } if (CC == CallingConv::Cold) { @@ -236,12 +235,12 @@ PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, : CSR_SVR32_ColdCC_RegMask)); } - return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask - : CSR_SVR464_RegMask) - : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask - : (Subtarget.hasSPE() - ? CSR_SVR432_SPE_RegMask - : CSR_SVR432_RegMask)); + return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask + : CSR_PPC64_RegMask) + : (Subtarget.hasAltivec() + ? CSR_SVR432_Altivec_RegMask + : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask + : CSR_SVR432_RegMask)); } const uint32_t* diff --git a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir index c529b91..35a0728 100644 --- a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir +++ b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir @@ -162,7 +162,7 @@ body: | $x3 = COPY %15 $x12 = COPY %3 MTCTR8 %3, implicit-def $ctr8 - BCTRL8_LDinto_toc 24, $x1, csr_svr464_altivec, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x3, implicit $x12, implicit $x2, implicit-def $r1 + BCTRL8_LDinto_toc 24, $x1, csr_ppc64_altivec, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x3, implicit $x12, implicit $x2, implicit-def $r1 ADJCALLSTACKUP 32, 0, implicit-def dead $r1, implicit $r1 bb.5.for.inc: diff --git a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir index aaf5b51..738aa1d 100644 --- a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir +++ b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir @@ -208,7 +208,7 @@ body: | $x3 = COPY %15 $x12 = COPY %3 MTCTR8 %3, implicit-def $ctr8 - BCTRL8_LDinto_toc 24, $x1, csr_svr464_altivec, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x3, implicit $x12, implicit $x2, implicit-def $r1 + BCTRL8_LDinto_toc 24, $x1, csr_ppc64_altivec, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x3, implicit $x12, implicit $x2, implicit-def $r1 ADJCALLSTACKUP 32, 0, implicit-def dead $r1, implicit $r1 bb.5.for.inc: diff --git a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir index 517f4c2..39ffbeec 100644 --- a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir +++ b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -79,7 +79,7 @@ body: | $x29 = ADDI8 killed $x3, -48 $x3 = ADDIStocHA8 $x2, @tasklist_lock $x3 = LDtocL @tasklist_lock, killed $x3, implicit $x2 :: (load 8 from got) - BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 + BL8_NOP @__raw_read_unlock, csr_ppc64_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 $r3 = LI 0 STW killed $r3, 0, killed $x30 :: (volatile store 4 into %ir.p2) INLINEASM &"#compiler barrier", 25 diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll index ee7ac53..10d9751 100644 --- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll +++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll @@ -33,7 +33,7 @@ entry: ; 64BIT: $x4 = LI8 97 ; 64BIT: $x5 = LI8 97 ; 64BIT: $x6 = LI8 97 -; 64BIT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1 +; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 define signext i8 @test_chars(i8 signext %c1, i8 signext %c2, i8 signext %c3, i8 signext %c4) { @@ -90,7 +90,7 @@ entry: ; 64BIT: $x4 = LI8 225 ; 64BIT: $x5 = LI8 97 ; 64BIT: $x6 = LI8 -31 -; 64BIT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1 +; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 define signext i8 @test_chars_mix(i8 signext %c1, i8 zeroext %c2, i8 zeroext %c3, i8 signext %c4) { @@ -165,7 +165,7 @@ entry: ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: $x3 = LI8 1 -; 64BIT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1 +; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 define void @test_i1zext(i1 zeroext %b) { @@ -249,7 +249,7 @@ entry: ; 64BIT: $x8 = LI8 1 ; 64BIT: $x9 = LI8 1 ; 64BIT: $x10 = LI8 1 -; 64BIT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3 +; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 define void @call_test_i64() { @@ -277,7 +277,7 @@ entry: ; 64BIT: $x4 = LI8 2 ; 64BIT: $x5 = LI8 3 ; 64BIT: $x6 = LI8 4 -; 64BIT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1 +; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 define i64 @test_i64(i64 %a, i64 %b, i64 %c, i64 %d) { @@ -329,7 +329,7 @@ entry: ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: renamable $x3 = ADDI8 %stack.0.b, 0 -; 64BIT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 +; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 define void @test_int_ptr(i32* %a) { @@ -390,7 +390,7 @@ declare i32 @call_test_bool(i1 zeroext) ; 64BIT-NEXT: bb.0.entry: ; 64BIT-NEXT: liveins: $x3 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3 +; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 @f1 = global float 0.000000e+00, align 4 @@ -418,7 +418,7 @@ entry: ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: $f2 = COPY renamable $f1 ; 64BIT-NEXT: $f3 = COPY renamable $f1 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 define float @test_floats(float %f1, float %f2, float %f3) { @@ -524,7 +524,7 @@ entry: ; 64BIT-DAG: $f11 = COPY renamable $f1 ; 64BIT-DAG: $f12 = COPY renamable $f1 ; 64BIT-DAG: $f13 = COPY renamable $f1 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1 ; ASM64PWR4: stdu 1, -160(1) @@ -615,7 +615,7 @@ entry: ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: $x4 = LI8 1 ; 64BIT-NEXT: $x6 = LI8 97 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x4, implicit $f2, implicit killed $x6, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x4, implicit $f2, implicit killed $x6, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 define i32 @test_mix(float %f, i32 signext %i, double %d, i8 signext %c) { @@ -742,7 +742,7 @@ declare void @test_vararg(i32, ...) ; 64BIT-NEXT: renamable $x5 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]]) ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: $x3 = LI8 42 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; ASM64PWR4: stdu 1, -128(1) @@ -812,7 +812,7 @@ entry: ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: $x3 = LI8 42 ; 64BIT-NEXT: $x5 = LI8 42 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; ASM64PWR4: stdu 1, -128(1) @@ -885,7 +885,7 @@ entry: ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: $x3 = LI8 42 ; 64BIT-NEXT: $x5 = LI8 42 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; ASM64PWR4: stdu 1, -128(1) @@ -935,7 +935,7 @@ entry: ; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]]) ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: $x3 = LI8 42 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; ASM64PWR4: stdu 1, -128(1) @@ -1051,7 +1051,7 @@ declare void @test_stackarg_int(i32, i32, i32, i32, i32, i32, i32, i32, i8 zeroe ; 64BIT-DAG: renamable $x[[REGLLI:[0-9]+]] = LD 0, killed renamable $x[[REGLLIADDR]] :: (dereferenceable load 8 from @lli) ; 64BIT-DAG: STD killed renamable $x[[REGLLI]], 136, $x1 :: (store 8) ; 64BIT-DAG: STD renamable $x[[REGI]], 144, $x1 :: (store 8) -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. @@ -1151,7 +1151,7 @@ declare void @test_stackarg_float(i32, i32, i32, i32, i32, i32, i32, i32, float, ; 64BIT-DAG: renamable $f2 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load 8 from @d) ; 64BIT-DAG: STFS renamable $f1, 112, $x1 :: (store 4) ; 64BIT-DAG: STFD renamable $f2, 120, $x1 :: (store 8) -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. @@ -1232,7 +1232,7 @@ declare void @test_stackarg_float2(i32, i32, i32, i32, i32, i32, ...) ; 64BIT-DAG: renamable $f1 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d) ; 64BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0) ; 64BIT-DAG: renamable $x9 = LD 0, %stack.0 :: (load 8 from %stack.0) -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. @@ -1325,7 +1325,7 @@ declare void @test_stackarg_float3(i32, i32, i32, i32, i32, i32, i32, ...) ; 64BIT-DAG: STFS renamable $f2, 112, $x1 :: (store 4) ; 64BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0) ; 64BIT-DAG: renamable $x10 = LD 0, %stack.0 :: (load 8 from %stack.0) -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1 @@ -1547,7 +1547,7 @@ entry: ; 64BIT-DAG: renamable $x[[REGI:[0-9]+]] = LWZ8 0, killed renamable $x[[REGIADDR]] :: (dereferenceable load 4 from @i1) ; 64BIT-DAG: STD killed renamable $x[[REGI]], 168, $x1 :: (store 8) ; 64BIT-DAG: ADJCALLSTACKDOWN 176, 0, implicit-def dead $r1, implicit $r1 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3 ; 64BIT-NEXT: ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm @@ -1714,7 +1714,7 @@ define void @call_test_i1_stack() { ; 64BIT-DAG: $x10 = LI8 8 ; 64BIT-DAG: renamable $x[[REGBOOLADDR:[0-9]+]] = LI8 1 ; 64BIT-DAG: STD killed renamable $x[[REGBOOLADDR]], 112, $x1 :: (store 8) -; 64BIT-DAG: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 +; 64BIT-DAG: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 ; 64BIT-DAG: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1 ; CHECKASM-LABEL: .call_test_i1_stack: @@ -1915,7 +1915,7 @@ entry: ; 64BIT-DAG: renamable $f11 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load 8 from constant-pool) ; 64BIT-DAG: renamable $f12 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load 8 from constant-pool) ; 64BIT-DAG: renamable $f13 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load 8 from constant-pool) -; 64BIT-DAG: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1 +; 64BIT-DAG: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1 ; 64BIT-NEXT: ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm @@ -2297,7 +2297,7 @@ define void @caller_mix() { ; 64BIT-DAG: STD killed renamable $x[[REG13:[0-9]+]], 200, $x1 :: (store 8) ; 64BIT-DAG: STD killed renamable $x[[REG14:[0-9]+]], 208, $x1 :: (store 8) ; 64BIT-DAG: STD killed renamable $x[[REG15:[0-9]+]], 216, $x1 :: (store 8) -; 64BIT-DAG: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $x3 +; 64BIT-DAG: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $x3 ; 64BIT-NEXT: ADJCALLSTACKUP 224, 0, implicit-def dead $r1, implicit $r1 ; CHEKASM-LABEL: .mix_floats_caller: diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll index 6ff8fff..52a4476 100644 --- a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll +++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll @@ -50,7 +50,7 @@ entry: ; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load 8 from got) ; 64BIT-NEXT: renamable $x3 = LBZ8 0, killed renamable $x[[REG]] :: (load 1) ; 64BIT-NEXT: renamable $x3 = RLDICR killed renamable $x3, 56, 7 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; ASM64: std 0, 16(1) @@ -160,7 +160,7 @@ entry: ; 64BIT-DAG: renamable $x5 = RLDICR killed renamable $x[[REG3]], 48, 15 ; 64BIT-DAG: $f2 = COPY renamable $f1 ; 64BIT-DAG: $x7 = LI8 43 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x5, implicit killed $f2, implicit killed $x7, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x5, implicit killed $f2, implicit killed $x7, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. @@ -280,7 +280,7 @@ entry: ; 64BIT-DAG: renamable $x10 = RLDIMI killed renamable $x10, killed renamable $x[[REG1]], 48, 0 ; 64BIT-DAG: $x[[REG3:[0-9]+]] = LI8 42 ; 64BIT-DAG: STD killed renamable $x[[REG3]], 112, $x1 :: (store 8) -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $x10, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $x10, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. @@ -379,7 +379,7 @@ entry: ; 64BIT-DAG: renamable $x[[LD2:[0-9]+]] = LWZ8 0, %stack.1.s4a :: (load 4 from %stack.1.s4a, align 8) ; 64BIT-DAG: renamable $x3 = RLDICR killed renamable $x[[LD1]], 32, 31 ; 64BIT-DAG: renamable $x4 = RLDICR killed renamable $x[[LD2]], 32, 31 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; ASM64: stdu 1, -128(1) @@ -500,7 +500,7 @@ declare zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1) ; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1) ; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7 ; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. @@ -555,7 +555,7 @@ declare zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1) ; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2) ; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15 ; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. @@ -616,7 +616,7 @@ declare zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1) ; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23 ; 64BIT-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15 ; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. @@ -667,7 +667,7 @@ declare zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1) ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got) ; 64BIT-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8) -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; ASM64: stdu 1, -112(1) @@ -728,7 +728,7 @@ declare zeroext i8 @test_byval_32Byte(%struct.S32* byval(%struct.S32) align 1 %s ; 64BIT-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8) ; 64BIT-DAG: renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load 8) ; 64BIT-DAG: renamable $x6 = LD 24, renamable $x[[REGADDR]] :: (load 8) -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; ASM64: stdu 1, -112(1) @@ -803,7 +803,7 @@ declare zeroext i8 @test_byval_31Byte(%struct.S31* byval(%struct.S31) align 1) ; 64BIT-DAG: renamable $x6 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23 ; 64BIT-DAG: renamable $x6 = RLWIMI8 killed renamable $x6, killed renamable $x[[REG2]], 16, 0, 15 ; 64BIT-DAG: renamable $x6 = RLDIMI killed renamable $x6, killed renamable $x[[REG1]], 32, 0 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; ASM64: stdu 1, -112(1) @@ -859,7 +859,7 @@ declare i32 @test_byval_homogeneous_float_struct(%struct.F* byval(%struct.F) ali ; 64BIT-DAG: renamable $x3 = LD 0, %stack.0.s :: (load 8 from %stack.0.s) ; 64BIT-DAG: renamable $x4 = LWZ8 8, %stack.0.s :: (load 4 from %stack.0.s + 8, align 8) ; 64BIT-DAG: renamable $x4 = RLDICR killed renamable $x4, 32, 31 -; 64BIT-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1, implicit-def $x3 +; 64BIT-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1, implicit-def $x3 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. diff --git a/llvm/test/CodeGen/PowerPC/aix-indirect-call.ll b/llvm/test/CodeGen/PowerPC/aix-indirect-call.ll index 977b2d5..2a0a6df 100644 --- a/llvm/test/CodeGen/PowerPC/aix-indirect-call.ll +++ b/llvm/test/CodeGen/PowerPC/aix-indirect-call.ll @@ -43,7 +43,7 @@ define signext i32 @callThroughPtr(i32 ()* nocapture) { ; MIR64-DAG: renamable $[[REG:x[0-9]+]] = LD 0, renamable $x3 :: (dereferenceable invariant load 8 from %ir.0) ; MIR64-DAG: $x2 = LD 8, killed renamable $x3 :: (dereferenceable invariant load 8 from %ir.0 + 8) ; MIR64-DAG: MTCTR8 killed renamable $[[REG]], implicit-def $ctr8 -; MIR64-NEXT: BCTRL8_LDinto_toc 40, $x1, csr_aix64, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x11, implicit $x2, implicit-def $r1, implicit-def $x3 +; MIR64-NEXT: BCTRL8_LDinto_toc 40, $x1, csr_ppc64, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x11, implicit $x2, implicit-def $r1, implicit-def $x3 ; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; CHECKASM-LABEL: .callThroughPtr: @@ -110,7 +110,7 @@ define void @callThroughPtrWithArgs(void (i32, i16, i64)* nocapture) { ; MIR64-DAG: $x3 = LI8 1 ; MIR64-DAG: $x4 = LI8 2 ; MIR64-DAG: $x5 = LI8 3 -; MIR64-NEXT: BCTRL8_LDinto_toc 40, $x1, csr_aix64, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x11, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1 +; MIR64-NEXT: BCTRL8_LDinto_toc 40, $x1, csr_ppc64, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x11, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1 ; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; CHECKASM-LABEL: .callThroughPtrWithArgs: diff --git a/llvm/test/CodeGen/PowerPC/aix-sret-param.ll b/llvm/test/CodeGen/PowerPC/aix-sret-param.ll index 0a2463f..8486e47 100644 --- a/llvm/test/CodeGen/PowerPC/aix-sret-param.ll +++ b/llvm/test/CodeGen/PowerPC/aix-sret-param.ll @@ -45,7 +45,7 @@ declare void @bar(%struct.T* sret) ; MIR64: bb.0.entry: ; MIR64-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; MIR64-NEXT: renamable $x3 = ADDI8 %stack.0.s, 0 -; MIR64-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 +; MIR64-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 @@ -78,7 +78,7 @@ declare void @bar(%struct.T* sret) ; MIR64: bb.0.entry: ; MIR64-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; MIR64-NEXT: renamable $x3 = ADDI8 %stack.0.t, 0 -; MIR64-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 +; MIR64-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 diff --git a/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll index ed84cdd..f695481 100644 --- a/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll +++ b/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll @@ -134,7 +134,7 @@ declare void @test_byval_64Byte(%struct.S64* byval(%struct.S64) align 1) ; CHECK-DAG: renamable $x8 = LD 40, renamable $x[[REGADDR]] :: (load 8) ; CHECK-DAG: renamable $x9 = LD 48, renamable $x[[REGADDR]] :: (load 8) ; CHECK-DAG: renamable $x10 = LD 56, renamable $x[[REGADDR]] :: (load 8) -; CHECK-NEXT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 +; CHECK-NEXT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 ; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; CHECKASM-LABEL: .test_byval_64Byte: diff --git a/llvm/test/CodeGen/PowerPC/block-placement-1.mir b/llvm/test/CodeGen/PowerPC/block-placement-1.mir index 1f9b666..2610935 100644 --- a/llvm/test/CodeGen/PowerPC/block-placement-1.mir +++ b/llvm/test/CodeGen/PowerPC/block-placement-1.mir @@ -154,7 +154,7 @@ body: | $x1 = STDU $x1, -32, $x1 CFI_INSTRUCTION def_cfa_offset 32 CFI_INSTRUCTION offset $lr8, 16 - BL8_NOP @__cxa_rethrow, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 + BL8_NOP @__cxa_rethrow, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 ... --- @@ -220,7 +220,7 @@ body: | liveins: $r29 EH_LABEL - BL8_NOP @__cxa_rethrow, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 + BL8_NOP @__cxa_rethrow, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 EH_LABEL bb.2..noexc: @@ -240,9 +240,9 @@ body: | successors: %bb.11(0x7ffff800), %bb.6(0x00000800) liveins: $r29, $x3 - BL8_NOP @__cxa_begin_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 + BL8_NOP @__cxa_begin_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 EH_LABEL - BL8_NOP @__cxa_rethrow, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 + BL8_NOP @__cxa_rethrow, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 EH_LABEL B %bb.11 @@ -250,7 +250,7 @@ body: | successors: %bb.8(0x80000000) liveins: $r29, $x3, $x30 - BL8_NOP @__cxa_begin_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 + BL8_NOP @__cxa_begin_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 renamable $cr0 = CMPLWI killed renamable $r30, 2, implicit $x30 B %bb.8 @@ -268,14 +268,14 @@ body: | liveins: $r29, $x30 $x3 = OR8 killed $x30, $x30 - BL8_NOP @__cxa_begin_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit-def $r1, implicit-def dead $x3 - BL8_NOP @__cxa_end_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 + BL8_NOP @__cxa_begin_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit-def $r1, implicit-def dead $x3 + BL8_NOP @__cxa_end_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 bb.8.for.inc: successors: %bb.9(0x04000000), %bb.1(0x7c000000) liveins: $r29 - BL8_NOP @__cxa_end_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 + BL8_NOP @__cxa_end_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 renamable $r29 = nsw ADDI killed renamable $r29, -1 renamable $cr0 = CMPLWI renamable $r29, 0 BCC 68, killed renamable $cr0, %bb.1 @@ -292,9 +292,9 @@ body: | successors: liveins: $x30 - BL8_NOP @__cxa_end_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 + BL8_NOP @__cxa_end_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1 $x3 = OR8 killed $x30, $x30 - BL8_NOP @_Unwind_Resume, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit-def $r1 + BL8_NOP @_Unwind_Resume, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit-def $r1 bb.11.unreachable: diff --git a/llvm/test/CodeGen/PowerPC/licm-tocReg.ll b/llvm/test/CodeGen/PowerPC/licm-tocReg.ll index 246bf7f..faad41a 100644 --- a/llvm/test/CodeGen/PowerPC/licm-tocReg.ll +++ b/llvm/test/CodeGen/PowerPC/licm-tocReg.ll @@ -36,7 +36,7 @@ ; %x3 = COPY %21 ; %x12 = COPY %4 ; MTCTR8 %4, implicit-def %ctr8 -; BCTRL8_LDinto_toc 24, %x1, csr_svr464_altivec, implicit-def dead %lr8, implicit-def dead %x2, implicit %ctr8, implicit %rm, implicit %x3, implicit %x12, implicit %x2, implicit-def %r1, implicit-def %x3 +; BCTRL8_LDinto_toc 24, %x1, csr_ppc64_altivec, implicit-def dead %lr8, implicit-def dead %x2, implicit %ctr8, implicit %rm, implicit %x3, implicit %x12, implicit %x2, implicit-def %r1, implicit-def %x3 ; ADJCALLSTACKUP 32, 0, implicit-def dead %r1, implicit %r1 ; %22 = COPY %x3 ; %x3 = COPY %22 diff --git a/llvm/test/CodeGen/PowerPC/machine-backward-cp.mir b/llvm/test/CodeGen/PowerPC/machine-backward-cp.mir index 0374d55..3146683 100644 --- a/llvm/test/CodeGen/PowerPC/machine-backward-cp.mir +++ b/llvm/test/CodeGen/PowerPC/machine-backward-cp.mir @@ -287,11 +287,11 @@ body: | ; CHECK-LABEL: name: cross_call ; CHECK: liveins: $x2, $x3, $x20 ; CHECK: renamable $x20 = LI8 1024 - ; CHECK: BL8_NOP @foo, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit-def $x3, implicit $x2 + ; CHECK: BL8_NOP @foo, csr_ppc64_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit-def $x3, implicit $x2 ; CHECK: $x3 = COPY killed renamable $x20 ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3 renamable $x20 = LI8 1024 - BL8_NOP @foo, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit-def $x3, implicit $x2 + BL8_NOP @foo, csr_ppc64_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit-def $x3, implicit $x2 $x3 = COPY renamable killed $x20 BLR8 implicit $lr8, implicit undef $rm, implicit $x3 ... diff --git a/llvm/test/CodeGen/PowerPC/setcr_bc.mir b/llvm/test/CodeGen/PowerPC/setcr_bc.mir index 0d8fc97..e9d81da 100644 --- a/llvm/test/CodeGen/PowerPC/setcr_bc.mir +++ b/llvm/test/CodeGen/PowerPC/setcr_bc.mir @@ -90,7 +90,7 @@ body: | $x1 = STDU $x1, -48, $x1 STD killed $x30, 32, $x1 :: (store 8 into %fixed-stack.0, align 16) $x30 = OR8 $x3, $x3 - BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 + BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 renamable $cr0 = CMPLWI renamable $r3, 0 BCC 76, killed renamable $cr0, %bb.2 @@ -99,7 +99,7 @@ body: | liveins: $x3 renamable $x3 = EXTSW_32_64 killed renamable $r3, implicit $x3 - BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 + BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 renamable $cr0gt = CRUNSET implicit-def $cr0 $x30 = OR8 killed $x3, $x3 BC killed renamable $cr0gt, %bb.5 @@ -109,7 +109,7 @@ body: | liveins: $x30 $x3 = LI8 0 - BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 + BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 bb.5.if.end: liveins: $x30 diff --git a/llvm/test/CodeGen/PowerPC/setcr_bc2.mir b/llvm/test/CodeGen/PowerPC/setcr_bc2.mir index 4c27452..87fff32 100644 --- a/llvm/test/CodeGen/PowerPC/setcr_bc2.mir +++ b/llvm/test/CodeGen/PowerPC/setcr_bc2.mir @@ -90,7 +90,7 @@ body: | $x1 = STDU $x1, -48, $x1 STD killed $x30, 32, $x1 :: (store 8 into %fixed-stack.0, align 16) $x30 = OR8 $x3, $x3 - BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 + BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 renamable $cr0 = CMPLWI renamable $r3, 0 BCC 76, killed renamable $cr0, %bb.2 @@ -99,7 +99,7 @@ body: | liveins: $x3 renamable $x3 = EXTSW_32_64 killed renamable $r3, implicit $x3 - BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 + BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 renamable $cr0gt = CRSET implicit-def $cr0 $x30 = OR8 killed $x3, $x3 BC killed renamable $cr0gt, %bb.5 @@ -109,7 +109,7 @@ body: | liveins: $x30 $x3 = LI8 0 - BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 + BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 bb.5.if.end: liveins: $x30, $cr0gt diff --git a/llvm/test/CodeGen/PowerPC/setcr_bc3.mir b/llvm/test/CodeGen/PowerPC/setcr_bc3.mir index ed05c48..579eeb7 100644 --- a/llvm/test/CodeGen/PowerPC/setcr_bc3.mir +++ b/llvm/test/CodeGen/PowerPC/setcr_bc3.mir @@ -64,7 +64,7 @@ body: | $x1 = STDU $x1, -48, $x1 STD killed $x30, 32, $x1 :: (store 8 into %fixed-stack.0, align 16) $x30 = OR8 $x3, $x3 - BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 + BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 renamable $cr0 = CMPLWI renamable $r3, 0 BCC 76, killed renamable $cr0, %bb.2 @@ -73,7 +73,7 @@ body: | liveins: $x3 renamable $x3 = EXTSW_32_64 killed renamable $r3, implicit $x3 - BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 + BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3 renamable $cr2un = CRSET $cr2gt = CROR $cr2un, $cr2un $x30 = OR8 killed $x3, $x3 @@ -85,7 +85,7 @@ body: | liveins: $x30 $x3 = LI8 0 - BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 + BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 bb.5: liveins: $x30, $cr0gt diff --git a/llvm/test/CodeGen/PowerPC/test_call_aix.ll b/llvm/test/CodeGen/PowerPC/test_call_aix.ll index ba363b7..cb2ebab 100644 --- a/llvm/test/CodeGen/PowerPC/test_call_aix.ll +++ b/llvm/test/CodeGen/PowerPC/test_call_aix.ll @@ -16,7 +16,7 @@ entry: ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT: BL8_NOP , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1 +; 64BIT: BL8_NOP , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; CHECK-LABEL: test_call @@ -39,7 +39,7 @@ entry: ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 -; 64BIT: BL8 , csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1 +; 64BIT: BL8 , csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; CHECK-LABEL: test_local_call -- 2.7.4