From b909eda0b36e6035b502807aad5df1f810822e82 Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Wed, 22 Feb 2023 19:34:54 +0100 Subject: [PATCH] ir3: Document that stc has higher DST upper bound than we defined Signed-off-by: Danylo Piliaiev Part-of: --- src/freedreno/ir3/tests/disasm.c | 3 +++ src/freedreno/isa/ir3-cat6.xml | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/freedreno/ir3/tests/disasm.c b/src/freedreno/ir3/tests/disasm.c index f4f327c..6e2f007 100644 --- a/src/freedreno/ir3/tests/disasm.c +++ b/src/freedreno/ir3/tests/disasm.c @@ -240,6 +240,9 @@ static const struct test { INSTR_6XX(c7020020_01800000, "stc.f32 c[32], r0.x, 1"), /* stc c[32], r0.x, 1 */ /* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */ INSTR_6XX(c7060020_03800000, "stc.u32 c[32], r0.x, 3"), /* stc c[32], r0.x, 3 */ + /* A660 EQP-VK.robustness.robustness2.push.notemplate.r32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag */ + /* TODO: stc has a similar to stsc DST range */ + /* INSTR_6XX(c702026e_0480025c, "stc.u32 c[366], r11.z, 4"), */ /* stc c[366], r11.z, 4 */ /* dEQP-VK.pipeline.monolithic.extended_dynamic_state.two_draws_static.stencil_state_face_both_single_gt_replace_clear_102_ref_103_depthfail */ INSTR_7XX(c7420000_0cc00000, "stsc.f32 c[0], 0, 12"), diff --git a/src/freedreno/isa/ir3-cat6.xml b/src/freedreno/isa/ir3-cat6.xml index 6291727..7a288d4 100644 --- a/src/freedreno/isa/ir3-cat6.xml +++ b/src/freedreno/isa/ir3-cat6.xml @@ -445,7 +445,8 @@ SOFTWARE. x - xxxxxxxxxxxxxx + xxxxx + xxxxxxxxxxxxxx 1 xxxxx -- 2.7.4