From b8e6319f3ef7f9e87cecefc73326dd025455c019 Mon Sep 17 00:00:00 2001
From: David Tellenbach <david.tellenbach@me.com>
Date: Sat, 23 Nov 2019 19:11:31 +0100
Subject: [PATCH] [NFC] [AArch64] Fix wrong documentation for
 IsStoreRegOffsetOp

---
 llvm/lib/Target/AArch64/AArch64SchedPredicates.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
index 028ad22..fc13b23 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
@@ -322,7 +322,7 @@ def IsLoadRegOffsetOp      : CheckOpcode<[PRFMroW, PRFMroX,
                                           LDRDroW, LDRDroX,
                                           LDRQroW, LDRQroX]>;
 
-// Identify whether an instruction is a load
+// Identify whether an instruction is a store
 // using the register offset addressing mode.
 def IsStoreRegOffsetOp     : CheckOpcode<[STRBBroW, STRBBroX,
                                           STRHHroW, STRHHroX,
-- 
2.7.4