From b8a9943dd4f35984507734e2ad21ad60e4f42d4e Mon Sep 17 00:00:00 2001
From: Doug Evans <dje@google.com>
Date: Thu, 5 Feb 1998 21:01:06 +0000
Subject: [PATCH] 	* Makefile.in (m32r.o): Depend on cpu.h 
 (extract.o): Pass -DSCACHE_P. 	* mloop.in (extract{16,32}): Update call to
 m32r_decode. 	* arch.h,cpu.h,cpuall.h,decode.[ch]: Regenerate. 	*
 extract.c,model.c,sem-switch.c,sem.c: Regenerate. 	* sim-main.h: #include
 "ansidecl.h". 	Don't include cpu-opc.h, done by arch.h. start-sanitize-m32rx 
 * Makefile.in (M32RX_OBJS): Build m32rx support now. 	(m32rx.o): New rule. 
 * m32r-sim.h (m32rx_h_cr_[gs]et): Define. 	* m32rx.c
 (m32rx_{fetch,store}_register): Update {get,set} of PC. 
 (m32rx_h_accums_get): New function. 	* mloopx.in: Update call to
 m32rx_decode.  Rewrite exec loop. 	*
 cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate. end-sanitize-m32rx

---
 sim/m32r/ChangeLog   |   23 +
 sim/m32r/Makefile.in |   29 +-
 sim/m32r/arch.h      |   22 +-
 sim/m32r/cpux.h      |  309 ++++----
 sim/m32r/decode.c    |  529 ++++++++++++++
 sim/m32r/decodex.c   |  601 ++++++++++++++++
 sim/m32r/extract.c   |   75 +-
 sim/m32r/m32rx.c     |  112 +++
 sim/m32r/mloopx.in   |  133 ++++
 sim/m32r/readx.c     |  332 ++++-----
 sim/m32r/sem.c       |  580 +++++++++++----
 sim/m32r/semx.c      | 1961 +++++++++++++++++++++++++-------------------------
 sim/m32r/sim-main.h  |    2 +-
 13 files changed, 3178 insertions(+), 1530 deletions(-)
 create mode 100644 sim/m32r/decode.c
 create mode 100644 sim/m32r/decodex.c
 create mode 100644 sim/m32r/m32rx.c
 create mode 100644 sim/m32r/mloopx.in

diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
index 9142801..c9ee966 100644
--- a/sim/m32r/ChangeLog
+++ b/sim/m32r/ChangeLog
@@ -1,3 +1,26 @@
+Thu Feb  5 12:44:31 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* Makefile.in (m32r.o): Depend on cpu.h
+	(extract.o): Pass -DSCACHE_P.
+	* mloop.in (extract{16,32}): Update call to m32r_decode.
+	* arch.h,cpu.h,cpuall.h,decode.[ch]: Regenerate.
+	* extract.c,model.c,sem-switch.c,sem.c: Regenerate.
+	* sim-main.h: #include "ansidecl.h".
+	Don't include cpu-opc.h, done by arch.h.
+start-sanitize-m32rx
+	* Makefile.in (M32RX_OBJS): Build m32rx support now.
+	(m32rx.o): New rule.
+	* m32r-sim.h (m32rx_h_cr_[gs]et): Define.
+	* m32rx.c (m32rx_{fetch,store}_register): Update {get,set} of PC.
+	(m32rx_h_accums_get): New function.
+	* mloopx.in: Update call to m32rx_decode.  Rewrite exec loop.
+	* cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
+end-sanitize-m32rx
+
+Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* configure: Regenerated to track ../common/aclocal.m4 changes.
+
 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* configure: Regenerated to track ../common/aclocal.m4 changes.
diff --git a/sim/m32r/Makefile.in b/sim/m32r/Makefile.in
index 458e443..1ad6bb4 100644
--- a/sim/m32r/Makefile.in
+++ b/sim/m32r/Makefile.in
@@ -66,48 +66,47 @@ OPS_INCLUDE_DEPS = \
 	$(srcdir)/../common/cgen-ops.h
 
 sim-if.o: sim-if.c $(INCLUDE_DEPS) $(srcdir)/../common/sim-core.h
-m32r.o: m32r.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS)
 
 arch.o: arch.c $(INCLUDE_DEPS) cpu-opc.h
 
 # M32R objs
 
+m32r.o: m32r.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
+
 # FIXME: Use of `mono' is wip.
 mloop.c: $(srcdir)/../common/genmloop.sh mloop.in Makefile
 	rm -f mloop.c
-	$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) -mono -scache -fast m32r $(srcdir)/mloop.in | sed -e 's/@cpu@/m32r/' -e 's/@CPU@/M32R/' >mloop.c
+	$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
+		-mono -scache -fast m32r $(srcdir)/mloop.in \
+		| sed -e 's/@cpu@/m32r/' -e 's/@CPU@/M32R/' >mloop.c
 mloop.o: mloop.c sem-switch.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
 
 decode.o: decode.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu-opc.h cpu.h
 extract.o: extract.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
+	$(CC) -c $(srcdir)/extract.c $(ALL_CFLAGS) -DSCACHE_P
 sem.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
 model.o: model.c $(INCLUDE_DEPS) cpu-opc.h cpu.h
 
-# wip
-#extr-cache.o: extract.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS)
-#	$(CC) -c $(srcdir)/extract.c -o extr-cache.o -DSCACHE_P $(ALL_CFLAGS)
-sem-cache.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
-	$(CC) -c $(srcdir)/sem.c -o sem-cache.o -DSCACHE_P $(ALL_CFLAGS)
+#sem-cache.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
+#	$(CC) -c $(srcdir)/sem.c -o sem-cache.o -DSCACHE_P $(ALL_CFLAGS)
 
 # start-sanitize-m32rx
 # M32RX objs
 
+m32rx.o: m32rx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
+
 # FIXME: Use of `mono' is wip.
 mloopx.c: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
 	rm -f mloopx.c
-	$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) -mono -no-scache -no-fast -parallel m32r $(srcdir)/mloopx.in | sed -e 's/@cpu@/m32rx/' -e 's/@CPU@/M32RX/' >mloopx.c
+	$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
+		-mono -no-scache -no-fast -no-parallel \
+		m32r $(srcdir)/mloopx.in \
+		| sed -e 's/@cpu@/m32rx/' -e 's/@CPU@/M32RX/' >mloopx.c
 mloopx.o: mloopx.c readx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
 
 decodex.o: decodex.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu-opc.h cpux.h
-extractx.o: extractx.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
 semx.o: semx.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
 modelx.o: modelx.c $(INCLUDE_DEPS) cpu-opc.h cpux.h
-
-# wip
-#extr-cache.o: extract.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS)
-#	$(CC) -c $(srcdir)/extract.c -o extr-cache.o -DSCACHE_P $(ALL_CFLAGS)
-semx-cache.o: semx.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
-	$(CC) -c $(srcdir)/semx.c -o semx-cache.o -DSCACHE_P $(ALL_CFLAGS)
 # end-sanitize-m32rx
 
 m32r-clean:
diff --git a/sim/m32r/arch.h b/sim/m32r/arch.h
index 989c9b2..57a7db1 100644
--- a/sim/m32r/arch.h
+++ b/sim/m32r/arch.h
@@ -1,5 +1,7 @@
 /* Simulator header for m32r.
 
+This file is machine generated with CGEN.
+
 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of the GNU Simulators.
@@ -23,25 +25,19 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifndef M32R_ARCH_H
 #define M32R_ARCH_H
 
-#define MAX_INSNS 166
+#include "m32r-opc.h"
 
 #define TARGET_BIG_ENDIAN 1
 
 /* Shorthand macro for fetching registers.  */
 #define CPU(x) (CPU_CGEN_HW (current_cpu)->x)
 
-/* Macros to determine which cpus are supported.  */
-#define HAVE_CPU_M32R
-/* start-sanitize-m32rx */
-/*#define HAVE_CPU_M32RX*/
-/* end-sanitize-m32rx */
-
 /* Enum declaration for mode types.  */
 typedef enum mode_type {
-  MODE_VM, MODE_BI, MODE_QI, MODE_HI,
-  MODE_SI, MODE_DI, MODE_UBI, MODE_UQI,
-  MODE_UHI, MODE_USI, MODE_UDI, MODE_SF,
-  MODE_DF, MODE_XF, MODE_TF, MODE_MAX
+  MODE_VM, MODE_BI, MODE_QI, MODE_HI
+ , MODE_SI, MODE_DI, MODE_UBI, MODE_UQI
+ , MODE_UHI, MODE_USI, MODE_UDI, MODE_SF
+ , MODE_DF, MODE_XF, MODE_TF, MODE_MAX
 } MODE_TYPE;
 
 #define MAX_MODES ((int) MODE_MAX)
@@ -58,8 +54,8 @@ typedef enum model_type {
 
 /* Enum declaration for unit types.  */
 typedef enum unit_type {
-  UNIT_NONE, UNIT_M32R_D_U_STORE, UNIT_M32R_D_U_LOAD, UNIT_M32R_D_U_EXEC,
-  UNIT_TEST_U_EXEC, UNIT_M32RX_U_EXEC, UNIT_MAX
+  UNIT_NONE, UNIT_M32R_D_U_STORE, UNIT_M32R_D_U_LOAD, UNIT_M32R_D_U_EXEC
+ , UNIT_TEST_U_EXEC, UNIT_M32RX_U_EXEC, UNIT_MAX
 } UNIT_TYPE;
 
 #define MAX_UNITS (1)
diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
index 37332b5..c647d46 100644
--- a/sim/m32r/cpux.h
+++ b/sim/m32r/cpux.h
@@ -1,5 +1,7 @@
 /* CPU family header for m32rx.
 
+This file is machine generated with CGEN.
+
 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of the GNU Simulators.
@@ -50,12 +52,16 @@ typedef struct {
   DI h_accum;
 #define GET_H_ACCUM() CPU (h_accum)
 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
+/* start-sanitize-m32rx */
   /* accumulators */
   DI h_accums[2];
+/* end-sanitize-m32rx */
 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
+/* start-sanitize-m32rx */
   /* abort flag */
   UBI h_abort;
+/* end-sanitize-m32rx */
 #define GET_H_ABORT() CPU (h_abort)
 #define SET_H_ABORT(x) (CPU (h_abort) = (x))
   /* condition bit */
@@ -96,8 +102,7 @@ typedef struct {
 #define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
 } M32RX_CPU_DATA;
 
-/* FIXME: length parm to decode() is currently unneeded.  */
-extern DECODE *m32rx_decode (SIM_CPU *, insn_t /*, int*/);
+extern DECODE *m32rx_decode (SIM_CPU *, PCADDR, insn_t);
 
 /* The ARGBUF struct.  */
 struct argbuf {
@@ -105,7 +110,9 @@ struct argbuf {
   unsigned int length;
   PCADDR addr;
   const struct cgen_insn *opcode;
-  /* unsigned long insn; - no longer needed */
+#if ! defined (SCACHE_P)
+  insn_t insn;
+#endif
   /* cpu specific data follows */
   union {
     struct { /* e.g. add $dr,$sr */
@@ -240,88 +247,83 @@ struct argbuf {
       UINT f_r1;
       HI f_simm16;
     } fmt_33_ldi16;
-    struct { /* e.g. machi $src1,$src2 */
-      UINT f_r1;
-      UINT f_r2;
-    } fmt_34_machi;
     struct { /* e.g. machi $src1,$src2,$acc */
       UINT f_r1;
       UINT f_acc;
       UINT f_r2;
-    } fmt_35_machi_a;
+    } fmt_34_machi_a;
     struct { /* e.g. mulhi $src1,$src2,$acc */
       UINT f_r1;
       UINT f_acc;
       UINT f_r2;
-    } fmt_36_mulhi_a;
+    } fmt_35_mulhi_a;
     struct { /* e.g. mv $dr,$sr */
       UINT f_r1;
       UINT f_r2;
-    } fmt_37_mv;
-    struct { /* e.g. mvfachi $dr */
-      UINT f_r1;
-    } fmt_38_mvfachi;
+    } fmt_36_mv;
     struct { /* e.g. mvfachi $dr,$accs */
       UINT f_r1;
       UINT f_accs;
-    } fmt_39_mvfachi_a;
+    } fmt_37_mvfachi_a;
     struct { /* e.g. mvfc $dr,$scr */
       UINT f_r1;
       UINT f_r2;
-    } fmt_40_mvfc;
-    struct { /* e.g. mvtachi $src1 */
-      UINT f_r1;
-    } fmt_41_mvtachi;
+    } fmt_38_mvfc;
     struct { /* e.g. mvtachi $src1,$accs */
       UINT f_r1;
       UINT f_accs;
-    } fmt_42_mvtachi_a;
+    } fmt_39_mvtachi_a;
     struct { /* e.g. mvtc $sr,$dcr */
       UINT f_r1;
       UINT f_r2;
-    } fmt_43_mvtc;
+    } fmt_40_mvtc;
     struct { /* e.g. nop */
       int empty;
-    } fmt_44_nop;
-    struct { /* e.g. rac */
-      int empty;
-    } fmt_45_rac;
+    } fmt_41_nop;
     struct { /* e.g. rac $accs */
       UINT f_accs;
-    } fmt_46_rac_a;
-    struct { /* e.g. seth $dr,$hi16 */
+    } fmt_42_rac_a;
+    struct { /* e.g. rte */
+      int empty;
+    } fmt_43_rte;
+    struct { /* e.g. seth $dr,#$hi16 */
       UINT f_r1;
       UHI f_hi16;
-    } fmt_47_seth;
+    } fmt_44_seth;
     struct { /* e.g. slli $dr,#$uimm5 */
       UINT f_r1;
       USI f_uimm5;
-    } fmt_48_slli;
+    } fmt_45_slli;
     struct { /* e.g. st $src1,@($slo16,$src2) */
       UINT f_r1;
       UINT f_r2;
       HI f_simm16;
-    } fmt_49_st_d;
+    } fmt_46_st_d;
     struct { /* e.g. trap #$uimm4 */
       USI f_uimm4;
-    } fmt_50_trap;
+    } fmt_47_trap;
     struct { /* e.g. satb $dr,$src2 */
       UINT f_r1;
       UINT f_r2;
-    } fmt_51_satb;
-    struct { /* e.g. pcmpbz $src2 */
+    } fmt_48_satb;
+    struct { /* e.g. sat $dr,$src2 */
+      UINT f_r1;
       UINT f_r2;
-    } fmt_52_pcmpbz;
+    } fmt_49_sat;
     struct { /* e.g. sadd */
       int empty;
-    } fmt_53_sadd;
+    } fmt_50_sadd;
     struct { /* e.g. macwu1 $src1,$src2 */
       UINT f_r1;
       UINT f_r2;
-    } fmt_54_macwu1;
+    } fmt_51_macwu1;
+    struct { /* e.g. msblo $src1,$src2 */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_52_msblo;
     struct { /* e.g. sc */
       int empty;
-    } fmt_55_sc;
+    } fmt_53_sc;
   } fields;
 #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
   unsigned long h_gr_get;
@@ -840,21 +842,7 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 
-#define EXTRACT_FMT_34_MACHI_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_FMT_34_MACHI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-
-#define EXTRACT_FMT_35_MACHI_A_VARS \
+#define EXTRACT_FMT_34_MACHI_A_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -862,7 +850,7 @@ struct scache {
   UINT f_op23; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_35_MACHI_A_CODE \
+#define EXTRACT_FMT_34_MACHI_A_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -870,7 +858,7 @@ struct scache {
   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_36_MULHI_A_VARS \
+#define EXTRACT_FMT_35_MULHI_A_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -878,7 +866,7 @@ struct scache {
   UINT f_op23; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_36_MULHI_A_CODE \
+#define EXTRACT_FMT_35_MULHI_A_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -886,35 +874,21 @@ struct scache {
   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_37_MV_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_FMT_37_MV_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-
-#define EXTRACT_FMT_38_MVFACHI_VARS \
+#define EXTRACT_FMT_36_MV_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_38_MVFACHI_CODE \
+#define EXTRACT_FMT_36_MV_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_39_MVFACHI_A_VARS \
+#define EXTRACT_FMT_37_MVFACHI_A_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -922,7 +896,7 @@ struct scache {
   UINT f_accs; \
   UINT f_op3; \
   unsigned int length;
-#define EXTRACT_FMT_39_MVFACHI_A_CODE \
+#define EXTRACT_FMT_37_MVFACHI_A_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -930,35 +904,21 @@ struct scache {
   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
 
-#define EXTRACT_FMT_40_MVFC_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_FMT_40_MVFC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-
-#define EXTRACT_FMT_41_MVTACHI_VARS \
+#define EXTRACT_FMT_38_MVFC_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_41_MVTACHI_CODE \
+#define EXTRACT_FMT_38_MVFC_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_42_MVTACHI_A_VARS \
+#define EXTRACT_FMT_39_MVTACHI_A_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -966,7 +926,7 @@ struct scache {
   UINT f_accs; \
   UINT f_op3; \
   unsigned int length;
-#define EXTRACT_FMT_42_MVTACHI_A_CODE \
+#define EXTRACT_FMT_39_MVTACHI_A_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -974,65 +934,65 @@ struct scache {
   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
 
-#define EXTRACT_FMT_43_MVTC_VARS \
+#define EXTRACT_FMT_40_MVTC_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_43_MVTC_CODE \
+#define EXTRACT_FMT_40_MVTC_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_44_NOP_VARS \
+#define EXTRACT_FMT_41_NOP_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_44_NOP_CODE \
+#define EXTRACT_FMT_41_NOP_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_45_RAC_VARS \
+#define EXTRACT_FMT_42_RAC_A_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
-  UINT f_r2; \
+  UINT f_accs; \
+  UINT f_op3; \
   unsigned int length;
-#define EXTRACT_FMT_45_RAC_CODE \
+#define EXTRACT_FMT_42_RAC_A_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
+  f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
 
-#define EXTRACT_FMT_46_RAC_A_VARS \
+#define EXTRACT_FMT_43_RTE_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
-  UINT f_accs; \
-  UINT f_op3; \
+  UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_46_RAC_A_CODE \
+#define EXTRACT_FMT_43_RTE_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_47_SETH_VARS \
+#define EXTRACT_FMT_44_SETH_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -1040,7 +1000,7 @@ struct scache {
   UINT f_r2; \
   UINT f_hi16; \
   unsigned int length;
-#define EXTRACT_FMT_47_SETH_CODE \
+#define EXTRACT_FMT_44_SETH_CODE \
   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1048,21 +1008,21 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 
-#define EXTRACT_FMT_48_SLLI_VARS \
+#define EXTRACT_FMT_45_SLLI_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_shift_op2; \
   UINT f_uimm5; \
   unsigned int length;
-#define EXTRACT_FMT_48_SLLI_CODE \
+#define EXTRACT_FMT_45_SLLI_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
   f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
 
-#define EXTRACT_FMT_49_ST_D_VARS \
+#define EXTRACT_FMT_46_ST_D_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -1070,7 +1030,7 @@ struct scache {
   UINT f_r2; \
   int f_simm16; \
   unsigned int length;
-#define EXTRACT_FMT_49_ST_D_CODE \
+#define EXTRACT_FMT_46_ST_D_CODE \
   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1078,21 +1038,37 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 
-#define EXTRACT_FMT_50_TRAP_VARS \
+#define EXTRACT_FMT_47_TRAP_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_uimm4; \
   unsigned int length;
-#define EXTRACT_FMT_50_TRAP_CODE \
+#define EXTRACT_FMT_47_TRAP_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_51_SATB_VARS \
+#define EXTRACT_FMT_48_SATB_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  UINT f_uimm16; \
+  unsigned int length;
+#define EXTRACT_FMT_48_SATB_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_49_SAT_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -1100,7 +1076,7 @@ struct scache {
   UINT f_r2; \
   UINT f_uimm16; \
   unsigned int length;
-#define EXTRACT_FMT_51_SATB_CODE \
+#define EXTRACT_FMT_49_SAT_CODE \
   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1108,56 +1084,56 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 
-#define EXTRACT_FMT_52_PCMPBZ_VARS \
+#define EXTRACT_FMT_50_SADD_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_52_PCMPBZ_CODE \
+#define EXTRACT_FMT_50_SADD_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_53_SADD_VARS \
+#define EXTRACT_FMT_51_MACWU1_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_53_SADD_CODE \
+#define EXTRACT_FMT_51_MACWU1_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_54_MACWU1_VARS \
+#define EXTRACT_FMT_52_MSBLO_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_54_MACWU1_CODE \
+#define EXTRACT_FMT_52_MSBLO_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_55_SC_VARS \
+#define EXTRACT_FMT_53_SC_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_55_SC_CODE \
+#define EXTRACT_FMT_53_SC_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -1269,29 +1245,29 @@ struct parallel_exec {
       SI sr;
     } fmt_24_jmp;
     struct { /* e.g. ld $dr,@$sr */
-      UQI h_memory;
+      UQI h_memory_sr;
       SI sr;
     } fmt_25_ld;
     struct { /* e.g. ld $dr,@($slo16,$sr) */
-      UQI h_memory;
+      UQI h_memory_add_WI_sr_slo16;
       HI slo16;
       SI sr;
     } fmt_26_ld_d;
     struct { /* e.g. ldb $dr,@$sr */
-      UQI h_memory;
+      UQI h_memory_sr;
       SI sr;
     } fmt_27_ldb;
     struct { /* e.g. ldb $dr,@($slo16,$sr) */
-      UQI h_memory;
+      UQI h_memory_add_WI_sr_slo16;
       HI slo16;
       SI sr;
     } fmt_28_ldb_d;
     struct { /* e.g. ldh $dr,@$sr */
-      UQI h_memory;
+      UQI h_memory_sr;
       SI sr;
     } fmt_29_ldh;
     struct { /* e.g. ldh $dr,@($slo16,$sr) */
-      UQI h_memory;
+      UQI h_memory_add_WI_sr_slo16;
       HI slo16;
       SI sr;
     } fmt_30_ldh_d;
@@ -1304,85 +1280,82 @@ struct parallel_exec {
     struct { /* e.g. ldi $dr,$slo16 */
       HI slo16;
     } fmt_33_ldi16;
-    struct { /* e.g. machi $src1,$src2 */
-      DI accum;
-      SI src1;
-      SI src2;
-    } fmt_34_machi;
     struct { /* e.g. machi $src1,$src2,$acc */
       DI acc;
       SI src1;
       SI src2;
-    } fmt_35_machi_a;
+    } fmt_34_machi_a;
     struct { /* e.g. mulhi $src1,$src2,$acc */
       SI src1;
       SI src2;
-    } fmt_36_mulhi_a;
+    } fmt_35_mulhi_a;
     struct { /* e.g. mv $dr,$sr */
       SI sr;
-    } fmt_37_mv;
-    struct { /* e.g. mvfachi $dr */
-      DI accum;
-    } fmt_38_mvfachi;
+    } fmt_36_mv;
     struct { /* e.g. mvfachi $dr,$accs */
       DI accs;
-    } fmt_39_mvfachi_a;
+    } fmt_37_mvfachi_a;
     struct { /* e.g. mvfc $dr,$scr */
       SI scr;
-    } fmt_40_mvfc;
-    struct { /* e.g. mvtachi $src1 */
-      DI accum;
-      SI src1;
-    } fmt_41_mvtachi;
+    } fmt_38_mvfc;
     struct { /* e.g. mvtachi $src1,$accs */
       DI accs;
       SI src1;
-    } fmt_42_mvtachi_a;
+    } fmt_39_mvtachi_a;
     struct { /* e.g. mvtc $sr,$dcr */
       SI sr;
-    } fmt_43_mvtc;
+    } fmt_40_mvtc;
     struct { /* e.g. nop */
       int empty;
-    } fmt_44_nop;
-    struct { /* e.g. rac */
-      DI accum;
-    } fmt_45_rac;
+    } fmt_41_nop;
     struct { /* e.g. rac $accs */
       DI accs;
-    } fmt_46_rac_a;
-    struct { /* e.g. seth $dr,$hi16 */
+    } fmt_42_rac_a;
+    struct { /* e.g. rte */
+      UBI h_bcond_0;
+      UBI h_bie_0;
+      SI h_bpc_0;
+      UBI h_bsm_0;
+    } fmt_43_rte;
+    struct { /* e.g. seth $dr,#$hi16 */
       UHI hi16;
-    } fmt_47_seth;
+    } fmt_44_seth;
     struct { /* e.g. slli $dr,#$uimm5 */
       SI dr;
       USI uimm5;
-    } fmt_48_slli;
+    } fmt_45_slli;
     struct { /* e.g. st $src1,@($slo16,$src2) */
       HI slo16;
       SI src1;
       SI src2;
-    } fmt_49_st_d;
+    } fmt_46_st_d;
     struct { /* e.g. trap #$uimm4 */
       USI uimm4;
-    } fmt_50_trap;
+    } fmt_47_trap;
     struct { /* e.g. satb $dr,$src2 */
-      int empty;
-    } fmt_51_satb;
-    struct { /* e.g. pcmpbz $src2 */
-      int empty;
-    } fmt_52_pcmpbz;
+      SI src2;
+    } fmt_48_satb;
+    struct { /* e.g. sat $dr,$src2 */
+      UBI condbit;
+      SI src2;
+    } fmt_49_sat;
     struct { /* e.g. sadd */
-      DI h_accums;
-      DI h_accums;
-    } fmt_53_sadd;
+      DI h_accums_0;
+      DI h_accums_1;
+    } fmt_50_sadd;
     struct { /* e.g. macwu1 $src1,$src2 */
-      DI h_accums;
+      DI h_accums_1;
+      SI src1;
+      SI src2;
+    } fmt_51_macwu1;
+    struct { /* e.g. msblo $src1,$src2 */
+      DI accum;
       SI src1;
       SI src2;
-    } fmt_54_macwu1;
+    } fmt_52_msblo;
     struct { /* e.g. sc */
       UBI condbit;
-    } fmt_55_sc;
+    } fmt_53_sc;
   } operands;
 };
 
diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
new file mode 100644
index 0000000..a779786
--- /dev/null
+++ b/sim/m32r/decode.c
@@ -0,0 +1,529 @@
+/* Simulator instruction decoder for m32r.
+
+This file is machine generated with CGEN.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU
+#define WANT_CPU_M32R
+
+#include "sim-main.h"
+#include "sim-xcat.h"
+#include "cpu-sim.h"
+#include "cpu-opc.h"
+
+/* FIXME: wip, may eventually only want one form so this would then go
+   away.  However, in the mean time, having both keeps a stable version
+   around while the cache version is being developed.
+   It may still be useful to allow two versions to exist though.  */
+#if WITH_SCACHE
+#define EX(fn) XCONCAT3 (m32r,_ex_,fn)
+#else
+#define EX(fn) 0
+#endif
+
+#if WITH_SEM_SWITCH_FULL
+#define FULL(fn) 0
+#else
+#define FULL(fn) XCONCAT3 (m32r,_sem_,fn)
+#endif
+
+#if WITH_SEM_SWITCH_FAST
+#define FAST(fn) 0
+#else
+#if WITH_SCACHE
+#define FAST(fn) XCONCAT3 (m32r,_semc_,fn)
+#else
+#define FAST(fn) 0
+#endif
+#endif
+
+/*#define DECODE M32R_DECODE*/
+
+/* The decode_illegal case is currently non-static and the generator doesn't
+   prepend m32r_, so simplify things by handling it here.  */
+#define decode_illegal m32r_decode_illegal
+
+static DECODE decode_add = { M32R_INSN_ADD, & m32r_cgen_insn_table_entries[M32R_INSN_ADD], EX (fmt_0_add), FULL (add), FAST (add) };
+static DECODE decode_add3 = { M32R_INSN_ADD3, & m32r_cgen_insn_table_entries[M32R_INSN_ADD3], EX (fmt_1_add3), FULL (add3), FAST (add3) };
+static DECODE decode_and = { M32R_INSN_AND, & m32r_cgen_insn_table_entries[M32R_INSN_AND], EX (fmt_0_add), FULL (and), FAST (and) };
+static DECODE decode_and3 = { M32R_INSN_AND3, & m32r_cgen_insn_table_entries[M32R_INSN_AND3], EX (fmt_2_and3), FULL (and3), FAST (and3) };
+static DECODE decode_or = { M32R_INSN_OR, & m32r_cgen_insn_table_entries[M32R_INSN_OR], EX (fmt_0_add), FULL (or), FAST (or) };
+static DECODE decode_or3 = { M32R_INSN_OR3, & m32r_cgen_insn_table_entries[M32R_INSN_OR3], EX (fmt_3_or3), FULL (or3), FAST (or3) };
+static DECODE decode_xor = { M32R_INSN_XOR, & m32r_cgen_insn_table_entries[M32R_INSN_XOR], EX (fmt_0_add), FULL (xor), FAST (xor) };
+static DECODE decode_xor3 = { M32R_INSN_XOR3, & m32r_cgen_insn_table_entries[M32R_INSN_XOR3], EX (fmt_2_and3), FULL (xor3), FAST (xor3) };
+static DECODE decode_addi = { M32R_INSN_ADDI, & m32r_cgen_insn_table_entries[M32R_INSN_ADDI], EX (fmt_4_addi), FULL (addi), FAST (addi) };
+static DECODE decode_addv = { M32R_INSN_ADDV, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV], EX (fmt_0_add), FULL (addv), FAST (addv) };
+static DECODE decode_addv3 = { M32R_INSN_ADDV3, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV3], EX (fmt_5_addv3), FULL (addv3), FAST (addv3) };
+static DECODE decode_addx = { M32R_INSN_ADDX, & m32r_cgen_insn_table_entries[M32R_INSN_ADDX], EX (fmt_6_addx), FULL (addx), FAST (addx) };
+static DECODE decode_bc8 = { M32R_INSN_BC8, & m32r_cgen_insn_table_entries[M32R_INSN_BC8], EX (fmt_7_bc8), FULL (bc8), FAST (bc8) };
+static DECODE decode_bc24 = { M32R_INSN_BC24, & m32r_cgen_insn_table_entries[M32R_INSN_BC24], EX (fmt_8_bc24), FULL (bc24), FAST (bc24) };
+static DECODE decode_beq = { M32R_INSN_BEQ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQ], EX (fmt_9_beq), FULL (beq), FAST (beq) };
+static DECODE decode_beqz = { M32R_INSN_BEQZ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQZ], EX (fmt_10_beqz), FULL (beqz), FAST (beqz) };
+static DECODE decode_bgez = { M32R_INSN_BGEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGEZ], EX (fmt_10_beqz), FULL (bgez), FAST (bgez) };
+static DECODE decode_bgtz = { M32R_INSN_BGTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGTZ], EX (fmt_10_beqz), FULL (bgtz), FAST (bgtz) };
+static DECODE decode_blez = { M32R_INSN_BLEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLEZ], EX (fmt_10_beqz), FULL (blez), FAST (blez) };
+static DECODE decode_bltz = { M32R_INSN_BLTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLTZ], EX (fmt_10_beqz), FULL (bltz), FAST (bltz) };
+static DECODE decode_bnez = { M32R_INSN_BNEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BNEZ], EX (fmt_10_beqz), FULL (bnez), FAST (bnez) };
+static DECODE decode_bl8 = { M32R_INSN_BL8, & m32r_cgen_insn_table_entries[M32R_INSN_BL8], EX (fmt_11_bl8), FULL (bl8), FAST (bl8) };
+static DECODE decode_bl24 = { M32R_INSN_BL24, & m32r_cgen_insn_table_entries[M32R_INSN_BL24], EX (fmt_12_bl24), FULL (bl24), FAST (bl24) };
+static DECODE decode_bnc8 = { M32R_INSN_BNC8, & m32r_cgen_insn_table_entries[M32R_INSN_BNC8], EX (fmt_7_bc8), FULL (bnc8), FAST (bnc8) };
+static DECODE decode_bnc24 = { M32R_INSN_BNC24, & m32r_cgen_insn_table_entries[M32R_INSN_BNC24], EX (fmt_8_bc24), FULL (bnc24), FAST (bnc24) };
+static DECODE decode_bne = { M32R_INSN_BNE, & m32r_cgen_insn_table_entries[M32R_INSN_BNE], EX (fmt_9_beq), FULL (bne), FAST (bne) };
+static DECODE decode_bra8 = { M32R_INSN_BRA8, & m32r_cgen_insn_table_entries[M32R_INSN_BRA8], EX (fmt_13_bra8), FULL (bra8), FAST (bra8) };
+static DECODE decode_bra24 = { M32R_INSN_BRA24, & m32r_cgen_insn_table_entries[M32R_INSN_BRA24], EX (fmt_14_bra24), FULL (bra24), FAST (bra24) };
+static DECODE decode_cmp = { M32R_INSN_CMP, & m32r_cgen_insn_table_entries[M32R_INSN_CMP], EX (fmt_15_cmp), FULL (cmp), FAST (cmp) };
+static DECODE decode_cmpi = { M32R_INSN_CMPI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPI], EX (fmt_16_cmpi), FULL (cmpi), FAST (cmpi) };
+static DECODE decode_cmpu = { M32R_INSN_CMPU, & m32r_cgen_insn_table_entries[M32R_INSN_CMPU], EX (fmt_15_cmp), FULL (cmpu), FAST (cmpu) };
+static DECODE decode_cmpui = { M32R_INSN_CMPUI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPUI], EX (fmt_17_cmpui), FULL (cmpui), FAST (cmpui) };
+static DECODE decode_div = { M32R_INSN_DIV, & m32r_cgen_insn_table_entries[M32R_INSN_DIV], EX (fmt_18_div), FULL (div), FAST (div) };
+static DECODE decode_divu = { M32R_INSN_DIVU, & m32r_cgen_insn_table_entries[M32R_INSN_DIVU], EX (fmt_18_div), FULL (divu), FAST (divu) };
+static DECODE decode_rem = { M32R_INSN_REM, & m32r_cgen_insn_table_entries[M32R_INSN_REM], EX (fmt_18_div), FULL (rem), FAST (rem) };
+static DECODE decode_remu = { M32R_INSN_REMU, & m32r_cgen_insn_table_entries[M32R_INSN_REMU], EX (fmt_18_div), FULL (remu), FAST (remu) };
+static DECODE decode_jl = { M32R_INSN_JL, & m32r_cgen_insn_table_entries[M32R_INSN_JL], EX (fmt_19_jl), FULL (jl), FAST (jl) };
+static DECODE decode_jmp = { M32R_INSN_JMP, & m32r_cgen_insn_table_entries[M32R_INSN_JMP], EX (fmt_20_jmp), FULL (jmp), FAST (jmp) };
+static DECODE decode_ld = { M32R_INSN_LD, & m32r_cgen_insn_table_entries[M32R_INSN_LD], EX (fmt_21_ld), FULL (ld), FAST (ld) };
+static DECODE decode_ld_d = { M32R_INSN_LD_D, & m32r_cgen_insn_table_entries[M32R_INSN_LD_D], EX (fmt_22_ld_d), FULL (ld_d), FAST (ld_d) };
+static DECODE decode_ldb = { M32R_INSN_LDB, & m32r_cgen_insn_table_entries[M32R_INSN_LDB], EX (fmt_23_ldb), FULL (ldb), FAST (ldb) };
+static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDB_D], EX (fmt_24_ldb_d), FULL (ldb_d), FAST (ldb_d) };
+static DECODE decode_ldh = { M32R_INSN_LDH, & m32r_cgen_insn_table_entries[M32R_INSN_LDH], EX (fmt_25_ldh), FULL (ldh), FAST (ldh) };
+static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDH_D], EX (fmt_26_ldh_d), FULL (ldh_d), FAST (ldh_d) };
+static DECODE decode_ldub = { M32R_INSN_LDUB, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB], EX (fmt_23_ldb), FULL (ldub), FAST (ldub) };
+static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB_D], EX (fmt_24_ldb_d), FULL (ldub_d), FAST (ldub_d) };
+static DECODE decode_lduh = { M32R_INSN_LDUH, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH], EX (fmt_25_ldh), FULL (lduh), FAST (lduh) };
+static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH_D], EX (fmt_26_ldh_d), FULL (lduh_d), FAST (lduh_d) };
+static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_LD_PLUS], EX (fmt_21_ld), FULL (ld_plus), FAST (ld_plus) };
+static DECODE decode_ld24 = { M32R_INSN_LD24, & m32r_cgen_insn_table_entries[M32R_INSN_LD24], EX (fmt_27_ld24), FULL (ld24), FAST (ld24) };
+static DECODE decode_ldi8 = { M32R_INSN_LDI8, & m32r_cgen_insn_table_entries[M32R_INSN_LDI8], EX (fmt_28_ldi8), FULL (ldi8), FAST (ldi8) };
+static DECODE decode_ldi16 = { M32R_INSN_LDI16, & m32r_cgen_insn_table_entries[M32R_INSN_LDI16], EX (fmt_29_ldi16), FULL (ldi16), FAST (ldi16) };
+static DECODE decode_lock = { M32R_INSN_LOCK, & m32r_cgen_insn_table_entries[M32R_INSN_LOCK], EX (fmt_0_add), FULL (lock), FAST (lock) };
+static DECODE decode_machi = { M32R_INSN_MACHI, & m32r_cgen_insn_table_entries[M32R_INSN_MACHI], EX (fmt_30_machi), FULL (machi), FAST (machi) };
+static DECODE decode_maclo = { M32R_INSN_MACLO, & m32r_cgen_insn_table_entries[M32R_INSN_MACLO], EX (fmt_30_machi), FULL (maclo), FAST (maclo) };
+static DECODE decode_macwhi = { M32R_INSN_MACWHI, & m32r_cgen_insn_table_entries[M32R_INSN_MACWHI], EX (fmt_30_machi), FULL (macwhi), FAST (macwhi) };
+static DECODE decode_macwlo = { M32R_INSN_MACWLO, & m32r_cgen_insn_table_entries[M32R_INSN_MACWLO], EX (fmt_30_machi), FULL (macwlo), FAST (macwlo) };
+static DECODE decode_mul = { M32R_INSN_MUL, & m32r_cgen_insn_table_entries[M32R_INSN_MUL], EX (fmt_0_add), FULL (mul), FAST (mul) };
+static DECODE decode_mulhi = { M32R_INSN_MULHI, & m32r_cgen_insn_table_entries[M32R_INSN_MULHI], EX (fmt_15_cmp), FULL (mulhi), FAST (mulhi) };
+static DECODE decode_mullo = { M32R_INSN_MULLO, & m32r_cgen_insn_table_entries[M32R_INSN_MULLO], EX (fmt_15_cmp), FULL (mullo), FAST (mullo) };
+static DECODE decode_mulwhi = { M32R_INSN_MULWHI, & m32r_cgen_insn_table_entries[M32R_INSN_MULWHI], EX (fmt_15_cmp), FULL (mulwhi), FAST (mulwhi) };
+static DECODE decode_mulwlo = { M32R_INSN_MULWLO, & m32r_cgen_insn_table_entries[M32R_INSN_MULWLO], EX (fmt_15_cmp), FULL (mulwlo), FAST (mulwlo) };
+static DECODE decode_mv = { M32R_INSN_MV, & m32r_cgen_insn_table_entries[M32R_INSN_MV], EX (fmt_31_mv), FULL (mv), FAST (mv) };
+static DECODE decode_mvfachi = { M32R_INSN_MVFACHI, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACHI], EX (fmt_32_mvfachi), FULL (mvfachi), FAST (mvfachi) };
+static DECODE decode_mvfaclo = { M32R_INSN_MVFACLO, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACLO], EX (fmt_32_mvfachi), FULL (mvfaclo), FAST (mvfaclo) };
+static DECODE decode_mvfacmi = { M32R_INSN_MVFACMI, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACMI], EX (fmt_32_mvfachi), FULL (mvfacmi), FAST (mvfacmi) };
+static DECODE decode_mvfc = { M32R_INSN_MVFC, & m32r_cgen_insn_table_entries[M32R_INSN_MVFC], EX (fmt_33_mvfc), FULL (mvfc), FAST (mvfc) };
+static DECODE decode_mvtachi = { M32R_INSN_MVTACHI, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACHI], EX (fmt_34_mvtachi), FULL (mvtachi), FAST (mvtachi) };
+static DECODE decode_mvtaclo = { M32R_INSN_MVTACLO, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACLO], EX (fmt_34_mvtachi), FULL (mvtaclo), FAST (mvtaclo) };
+static DECODE decode_mvtc = { M32R_INSN_MVTC, & m32r_cgen_insn_table_entries[M32R_INSN_MVTC], EX (fmt_35_mvtc), FULL (mvtc), FAST (mvtc) };
+static DECODE decode_neg = { M32R_INSN_NEG, & m32r_cgen_insn_table_entries[M32R_INSN_NEG], EX (fmt_31_mv), FULL (neg), FAST (neg) };
+static DECODE decode_nop = { M32R_INSN_NOP, & m32r_cgen_insn_table_entries[M32R_INSN_NOP], EX (fmt_36_nop), FULL (nop), FAST (nop) };
+static DECODE decode_not = { M32R_INSN_NOT, & m32r_cgen_insn_table_entries[M32R_INSN_NOT], EX (fmt_31_mv), FULL (not), FAST (not) };
+static DECODE decode_rac = { M32R_INSN_RAC, & m32r_cgen_insn_table_entries[M32R_INSN_RAC], EX (fmt_37_rac), FULL (rac), FAST (rac) };
+static DECODE decode_rach = { M32R_INSN_RACH, & m32r_cgen_insn_table_entries[M32R_INSN_RACH], EX (fmt_37_rac), FULL (rach), FAST (rach) };
+static DECODE decode_rte = { M32R_INSN_RTE, & m32r_cgen_insn_table_entries[M32R_INSN_RTE], EX (fmt_38_rte), FULL (rte), FAST (rte) };
+static DECODE decode_seth = { M32R_INSN_SETH, & m32r_cgen_insn_table_entries[M32R_INSN_SETH], EX (fmt_39_seth), FULL (seth), FAST (seth) };
+static DECODE decode_sll = { M32R_INSN_SLL, & m32r_cgen_insn_table_entries[M32R_INSN_SLL], EX (fmt_0_add), FULL (sll), FAST (sll) };
+static DECODE decode_sll3 = { M32R_INSN_SLL3, & m32r_cgen_insn_table_entries[M32R_INSN_SLL3], EX (fmt_5_addv3), FULL (sll3), FAST (sll3) };
+static DECODE decode_slli = { M32R_INSN_SLLI, & m32r_cgen_insn_table_entries[M32R_INSN_SLLI], EX (fmt_40_slli), FULL (slli), FAST (slli) };
+static DECODE decode_sra = { M32R_INSN_SRA, & m32r_cgen_insn_table_entries[M32R_INSN_SRA], EX (fmt_0_add), FULL (sra), FAST (sra) };
+static DECODE decode_sra3 = { M32R_INSN_SRA3, & m32r_cgen_insn_table_entries[M32R_INSN_SRA3], EX (fmt_5_addv3), FULL (sra3), FAST (sra3) };
+static DECODE decode_srai = { M32R_INSN_SRAI, & m32r_cgen_insn_table_entries[M32R_INSN_SRAI], EX (fmt_40_slli), FULL (srai), FAST (srai) };
+static DECODE decode_srl = { M32R_INSN_SRL, & m32r_cgen_insn_table_entries[M32R_INSN_SRL], EX (fmt_0_add), FULL (srl), FAST (srl) };
+static DECODE decode_srl3 = { M32R_INSN_SRL3, & m32r_cgen_insn_table_entries[M32R_INSN_SRL3], EX (fmt_5_addv3), FULL (srl3), FAST (srl3) };
+static DECODE decode_srli = { M32R_INSN_SRLI, & m32r_cgen_insn_table_entries[M32R_INSN_SRLI], EX (fmt_40_slli), FULL (srli), FAST (srli) };
+static DECODE decode_st = { M32R_INSN_ST, & m32r_cgen_insn_table_entries[M32R_INSN_ST], EX (fmt_15_cmp), FULL (st), FAST (st) };
+static DECODE decode_st_d = { M32R_INSN_ST_D, & m32r_cgen_insn_table_entries[M32R_INSN_ST_D], EX (fmt_41_st_d), FULL (st_d), FAST (st_d) };
+static DECODE decode_stb = { M32R_INSN_STB, & m32r_cgen_insn_table_entries[M32R_INSN_STB], EX (fmt_15_cmp), FULL (stb), FAST (stb) };
+static DECODE decode_stb_d = { M32R_INSN_STB_D, & m32r_cgen_insn_table_entries[M32R_INSN_STB_D], EX (fmt_41_st_d), FULL (stb_d), FAST (stb_d) };
+static DECODE decode_sth = { M32R_INSN_STH, & m32r_cgen_insn_table_entries[M32R_INSN_STH], EX (fmt_15_cmp), FULL (sth), FAST (sth) };
+static DECODE decode_sth_d = { M32R_INSN_STH_D, & m32r_cgen_insn_table_entries[M32R_INSN_STH_D], EX (fmt_41_st_d), FULL (sth_d), FAST (sth_d) };
+static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_PLUS], EX (fmt_15_cmp), FULL (st_plus), FAST (st_plus) };
+static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_MINUS], EX (fmt_15_cmp), FULL (st_minus), FAST (st_minus) };
+static DECODE decode_sub = { M32R_INSN_SUB, & m32r_cgen_insn_table_entries[M32R_INSN_SUB], EX (fmt_0_add), FULL (sub), FAST (sub) };
+static DECODE decode_subv = { M32R_INSN_SUBV, & m32r_cgen_insn_table_entries[M32R_INSN_SUBV], EX (fmt_0_add), FULL (subv), FAST (subv) };
+static DECODE decode_subx = { M32R_INSN_SUBX, & m32r_cgen_insn_table_entries[M32R_INSN_SUBX], EX (fmt_6_addx), FULL (subx), FAST (subx) };
+static DECODE decode_trap = { M32R_INSN_TRAP, & m32r_cgen_insn_table_entries[M32R_INSN_TRAP], EX (fmt_42_trap), FULL (trap), FAST (trap) };
+static DECODE decode_unlock = { M32R_INSN_UNLOCK, & m32r_cgen_insn_table_entries[M32R_INSN_UNLOCK], EX (fmt_15_cmp), FULL (unlock), FAST (unlock) };
+DECODE m32r_decode_illegal = {
+  M32R_INSN_ILLEGAL, & m32r_cgen_insn_table_entries[0],
+  EX (illegal), FULL (illegal),
+  FAST (illegal)
+};
+
+/* The order must match that of `labels' in sem-switch.c.  */
+
+DECODE *m32r_decode_vars[] = {
+  & m32r_decode_illegal,
+  & decode_add,
+  & decode_add3,
+  & decode_and,
+  & decode_and3,
+  & decode_or,
+  & decode_or3,
+  & decode_xor,
+  & decode_xor3,
+  & decode_addi,
+  & decode_addv,
+  & decode_addv3,
+  & decode_addx,
+  & decode_bc8,
+  & decode_bc24,
+  & decode_beq,
+  & decode_beqz,
+  & decode_bgez,
+  & decode_bgtz,
+  & decode_blez,
+  & decode_bltz,
+  & decode_bnez,
+  & decode_bl8,
+  & decode_bl24,
+  & decode_bnc8,
+  & decode_bnc24,
+  & decode_bne,
+  & decode_bra8,
+  & decode_bra24,
+  & decode_cmp,
+  & decode_cmpi,
+  & decode_cmpu,
+  & decode_cmpui,
+  & decode_div,
+  & decode_divu,
+  & decode_rem,
+  & decode_remu,
+  & decode_jl,
+  & decode_jmp,
+  & decode_ld,
+  & decode_ld_d,
+  & decode_ldb,
+  & decode_ldb_d,
+  & decode_ldh,
+  & decode_ldh_d,
+  & decode_ldub,
+  & decode_ldub_d,
+  & decode_lduh,
+  & decode_lduh_d,
+  & decode_ld_plus,
+  & decode_ld24,
+  & decode_ldi8,
+  & decode_ldi16,
+  & decode_lock,
+  & decode_machi,
+  & decode_maclo,
+  & decode_macwhi,
+  & decode_macwlo,
+  & decode_mul,
+  & decode_mulhi,
+  & decode_mullo,
+  & decode_mulwhi,
+  & decode_mulwlo,
+  & decode_mv,
+  & decode_mvfachi,
+  & decode_mvfaclo,
+  & decode_mvfacmi,
+  & decode_mvfc,
+  & decode_mvtachi,
+  & decode_mvtaclo,
+  & decode_mvtc,
+  & decode_neg,
+  & decode_nop,
+  & decode_not,
+  & decode_rac,
+  & decode_rach,
+  & decode_rte,
+  & decode_seth,
+  & decode_sll,
+  & decode_sll3,
+  & decode_slli,
+  & decode_sra,
+  & decode_sra3,
+  & decode_srai,
+  & decode_srl,
+  & decode_srl3,
+  & decode_srli,
+  & decode_st,
+  & decode_st_d,
+  & decode_stb,
+  & decode_stb_d,
+  & decode_sth,
+  & decode_sth_d,
+  & decode_st_plus,
+  & decode_st_minus,
+  & decode_sub,
+  & decode_subv,
+  & decode_subx,
+  & decode_trap,
+  & decode_unlock,
+  0
+};
+
+/* The decoder needs a slightly different computed goto switch control.  */
+#ifdef __GNUC__
+#define DECODE_SWITCH(N, X) goto *labels_##N[X];
+#else
+#define DECODE_SWITCH(N, X) switch (X)
+#endif
+
+/* Given an instruction, return a pointer to its DECODE entry.  */
+
+DECODE *
+m32r_decode (current_cpu, pc, insn)
+     SIM_CPU *current_cpu;
+     PCADDR pc;
+     insn_t insn;
+{
+  {
+#ifdef __GNUC__
+    static void *labels_0[256] = {
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && case_0_28, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && case_0_87, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && case_0_95, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && case_0_112, && case_0_113, && case_0_114, && case_0_115, 
+      && case_0_116, && case_0_117, && case_0_118, && case_0_119, 
+      && case_0_120, && case_0_121, && case_0_122, && case_0_123, 
+      && case_0_124, && case_0_125, && case_0_126, && case_0_127, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && case_0_240, && case_0_241, && case_0_242, && case_0_243, 
+      && case_0_244, && case_0_245, && case_0_246, && case_0_247, 
+      && case_0_248, && case_0_249, && case_0_250, && case_0_251, 
+      && case_0_252, && case_0_253, && case_0_254, && case_0_255, 
+    };
+#endif
+    static DECODE *insns[256] = {
+      &decode_subv, &decode_subx, &decode_sub, &decode_neg, 
+      &decode_cmp, &decode_cmpu, &decode_illegal, &decode_illegal, 
+      &decode_addv, &decode_addx, &decode_add, &decode_not, 
+      &decode_and, &decode_xor, &decode_or, &decode_illegal, 
+      &decode_srl, &decode_illegal, &decode_sra, &decode_illegal, 
+      &decode_sll, &decode_illegal, &decode_mul, &decode_illegal, 
+      &decode_mv, &decode_mvfc, &decode_mvtc, &decode_illegal, 
+      0, &decode_rte, &decode_illegal, &decode_trap, 
+      &decode_stb, &decode_illegal, &decode_sth, &decode_illegal, 
+      &decode_st, &decode_unlock, &decode_st_plus, &decode_st_minus, 
+      &decode_ldb, &decode_ldub, &decode_ldh, &decode_lduh, 
+      &decode_ld, &decode_lock, &decode_ld_plus, &decode_illegal, 
+      &decode_mulhi, &decode_mullo, &decode_mulwhi, &decode_mulwlo, 
+      &decode_machi, &decode_maclo, &decode_macwhi, &decode_macwlo, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
+      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
+      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
+      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
+      &decode_srli, &decode_srli, &decode_srai, &decode_srai, 
+      &decode_slli, &decode_slli, &decode_illegal, 0, 
+      &decode_rach, &decode_rac, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, 0, 
+      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
+      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
+      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
+      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal, 
+      &decode_addv3, &decode_illegal, &decode_add3, &decode_illegal, 
+      &decode_and3, &decode_xor3, &decode_or3, &decode_illegal, 
+      &decode_div, &decode_divu, &decode_rem, &decode_remu, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal, 
+      &decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16, 
+      &decode_stb_d, &decode_illegal, &decode_sth_d, &decode_illegal, 
+      &decode_st_d, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_ldb_d, &decode_ldub_d, &decode_ldh_d, &decode_lduh_d, 
+      &decode_ld_d, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_beq, &decode_bne, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_beqz, &decode_bnez, &decode_bltz, &decode_bgez, 
+      &decode_blez, &decode_bgtz, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_seth, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
+      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
+      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
+      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+    };
+    unsigned int val;
+    val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
+    DECODE_SWITCH (0, val)
+      {
+      CASE (0, 28) :
+        {
+          static DECODE *insns[16] = {
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_jl, &decode_jmp, 
+          };
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          return insns[val];
+        }
+      CASE (0, 87) :
+        {
+          static DECODE *insns[16] = {
+            &decode_mvtachi, &decode_mvtaclo, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+          };
+          unsigned int val = (((insn >> 0) & (15 << 0)));
+          return insns[val];
+        }
+      CASE (0, 95) :
+        {
+          static DECODE *insns[16] = {
+            &decode_mvfachi, &decode_mvfaclo, &decode_mvfacmi, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+          };
+          unsigned int val = (((insn >> 0) & (15 << 0)));
+          return insns[val];
+        }
+      CASE (0, 112) :
+        {
+          static DECODE *insns[16] = {
+            &decode_nop, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8, 
+          };
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          return insns[val];
+        }
+      CASE (0, 113) : /* fall through */
+      CASE (0, 114) : /* fall through */
+      CASE (0, 115) : /* fall through */
+      CASE (0, 116) : /* fall through */
+      CASE (0, 117) : /* fall through */
+      CASE (0, 118) : /* fall through */
+      CASE (0, 119) : /* fall through */
+      CASE (0, 120) : /* fall through */
+      CASE (0, 121) : /* fall through */
+      CASE (0, 122) : /* fall through */
+      CASE (0, 123) : /* fall through */
+      CASE (0, 124) : /* fall through */
+      CASE (0, 125) : /* fall through */
+      CASE (0, 126) : /* fall through */
+      CASE (0, 127) :
+        {
+          static DECODE *insns[16] = {
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8, 
+          };
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          return insns[val];
+        }
+      CASE (0, 240) : /* fall through */
+      CASE (0, 241) : /* fall through */
+      CASE (0, 242) : /* fall through */
+      CASE (0, 243) : /* fall through */
+      CASE (0, 244) : /* fall through */
+      CASE (0, 245) : /* fall through */
+      CASE (0, 246) : /* fall through */
+      CASE (0, 247) : /* fall through */
+      CASE (0, 248) : /* fall through */
+      CASE (0, 249) : /* fall through */
+      CASE (0, 250) : /* fall through */
+      CASE (0, 251) : /* fall through */
+      CASE (0, 252) : /* fall through */
+      CASE (0, 253) : /* fall through */
+      CASE (0, 254) : /* fall through */
+      CASE (0, 255) :
+        {
+          static DECODE *insns[16] = {
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_bc24, &decode_bnc24, &decode_bl24, &decode_bra24, 
+          };
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          return insns[val];
+        }
+      DEFAULT (0) : return insns[val];
+      }
+    ENDSWITCH (0)
+  }
+}
diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
new file mode 100644
index 0000000..31c32af
--- /dev/null
+++ b/sim/m32r/decodex.c
@@ -0,0 +1,601 @@
+/* Simulator instruction decoder for m32r.
+
+This file is machine generated with CGEN.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU
+#define WANT_CPU_M32RX
+
+#include "sim-main.h"
+#include "sim-xcat.h"
+#include "cpu-sim.h"
+#include "cpu-opc.h"
+
+/* FIXME: wip, may eventually only want one form so this would then go
+   away.  However, in the mean time, having both keeps a stable version
+   around while the cache version is being developed.
+   It may still be useful to allow two versions to exist though.  */
+#if WITH_SCACHE
+#define EX(fn) XCONCAT3 (m32rx,_ex_,fn)
+#else
+#define EX(fn) 0
+#endif
+
+#if WITH_SEM_SWITCH_FULL
+#define FULL(fn) 0
+#else
+#define FULL(fn) XCONCAT3 (m32rx,_sem_,fn)
+#endif
+
+#if WITH_SEM_SWITCH_FAST
+#define FAST(fn) 0
+#else
+#if WITH_SCACHE
+#define FAST(fn) XCONCAT3 (m32rx,_semc_,fn)
+#else
+#define FAST(fn) 0
+#endif
+#endif
+
+/*#define DECODE M32RX_DECODE*/
+
+/* The decode_illegal case is currently non-static and the generator doesn't
+   prepend m32rx_, so simplify things by handling it here.  */
+#define decode_illegal m32rx_decode_illegal
+
+static DECODE decode_add = { M32R_INSN_ADD, & m32r_cgen_insn_table_entries[M32R_INSN_ADD], EX (fmt_0_add), FULL (add), FAST (add) };
+static DECODE decode_add3 = { M32R_INSN_ADD3, & m32r_cgen_insn_table_entries[M32R_INSN_ADD3], EX (fmt_1_add3), FULL (add3), FAST (add3) };
+static DECODE decode_and = { M32R_INSN_AND, & m32r_cgen_insn_table_entries[M32R_INSN_AND], EX (fmt_0_add), FULL (and), FAST (and) };
+static DECODE decode_and3 = { M32R_INSN_AND3, & m32r_cgen_insn_table_entries[M32R_INSN_AND3], EX (fmt_2_and3), FULL (and3), FAST (and3) };
+static DECODE decode_or = { M32R_INSN_OR, & m32r_cgen_insn_table_entries[M32R_INSN_OR], EX (fmt_0_add), FULL (or), FAST (or) };
+static DECODE decode_or3 = { M32R_INSN_OR3, & m32r_cgen_insn_table_entries[M32R_INSN_OR3], EX (fmt_3_or3), FULL (or3), FAST (or3) };
+static DECODE decode_xor = { M32R_INSN_XOR, & m32r_cgen_insn_table_entries[M32R_INSN_XOR], EX (fmt_0_add), FULL (xor), FAST (xor) };
+static DECODE decode_xor3 = { M32R_INSN_XOR3, & m32r_cgen_insn_table_entries[M32R_INSN_XOR3], EX (fmt_2_and3), FULL (xor3), FAST (xor3) };
+static DECODE decode_addi = { M32R_INSN_ADDI, & m32r_cgen_insn_table_entries[M32R_INSN_ADDI], EX (fmt_4_addi), FULL (addi), FAST (addi) };
+static DECODE decode_addv = { M32R_INSN_ADDV, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV], EX (fmt_0_add), FULL (addv), FAST (addv) };
+static DECODE decode_addv3 = { M32R_INSN_ADDV3, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV3], EX (fmt_5_addv3), FULL (addv3), FAST (addv3) };
+static DECODE decode_addx = { M32R_INSN_ADDX, & m32r_cgen_insn_table_entries[M32R_INSN_ADDX], EX (fmt_6_addx), FULL (addx), FAST (addx) };
+static DECODE decode_bc8 = { M32R_INSN_BC8, & m32r_cgen_insn_table_entries[M32R_INSN_BC8], EX (fmt_7_bc8), FULL (bc8), FAST (bc8) };
+static DECODE decode_bc24 = { M32R_INSN_BC24, & m32r_cgen_insn_table_entries[M32R_INSN_BC24], EX (fmt_8_bc24), FULL (bc24), FAST (bc24) };
+static DECODE decode_beq = { M32R_INSN_BEQ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQ], EX (fmt_9_beq), FULL (beq), FAST (beq) };
+static DECODE decode_beqz = { M32R_INSN_BEQZ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQZ], EX (fmt_10_beqz), FULL (beqz), FAST (beqz) };
+static DECODE decode_bgez = { M32R_INSN_BGEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGEZ], EX (fmt_10_beqz), FULL (bgez), FAST (bgez) };
+static DECODE decode_bgtz = { M32R_INSN_BGTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGTZ], EX (fmt_10_beqz), FULL (bgtz), FAST (bgtz) };
+static DECODE decode_blez = { M32R_INSN_BLEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLEZ], EX (fmt_10_beqz), FULL (blez), FAST (blez) };
+static DECODE decode_bltz = { M32R_INSN_BLTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLTZ], EX (fmt_10_beqz), FULL (bltz), FAST (bltz) };
+static DECODE decode_bnez = { M32R_INSN_BNEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BNEZ], EX (fmt_10_beqz), FULL (bnez), FAST (bnez) };
+static DECODE decode_bl8 = { M32R_INSN_BL8, & m32r_cgen_insn_table_entries[M32R_INSN_BL8], EX (fmt_11_bl8), FULL (bl8), FAST (bl8) };
+static DECODE decode_bl24 = { M32R_INSN_BL24, & m32r_cgen_insn_table_entries[M32R_INSN_BL24], EX (fmt_12_bl24), FULL (bl24), FAST (bl24) };
+static DECODE decode_bcl8 = { M32R_INSN_BCL8, & m32r_cgen_insn_table_entries[M32R_INSN_BCL8], EX (fmt_13_bcl8), FULL (bcl8), FAST (bcl8) };
+static DECODE decode_bcl24 = { M32R_INSN_BCL24, & m32r_cgen_insn_table_entries[M32R_INSN_BCL24], EX (fmt_14_bcl24), FULL (bcl24), FAST (bcl24) };
+static DECODE decode_bnc8 = { M32R_INSN_BNC8, & m32r_cgen_insn_table_entries[M32R_INSN_BNC8], EX (fmt_7_bc8), FULL (bnc8), FAST (bnc8) };
+static DECODE decode_bnc24 = { M32R_INSN_BNC24, & m32r_cgen_insn_table_entries[M32R_INSN_BNC24], EX (fmt_8_bc24), FULL (bnc24), FAST (bnc24) };
+static DECODE decode_bne = { M32R_INSN_BNE, & m32r_cgen_insn_table_entries[M32R_INSN_BNE], EX (fmt_9_beq), FULL (bne), FAST (bne) };
+static DECODE decode_bra8 = { M32R_INSN_BRA8, & m32r_cgen_insn_table_entries[M32R_INSN_BRA8], EX (fmt_15_bra8), FULL (bra8), FAST (bra8) };
+static DECODE decode_bra24 = { M32R_INSN_BRA24, & m32r_cgen_insn_table_entries[M32R_INSN_BRA24], EX (fmt_16_bra24), FULL (bra24), FAST (bra24) };
+static DECODE decode_bncl8 = { M32R_INSN_BNCL8, & m32r_cgen_insn_table_entries[M32R_INSN_BNCL8], EX (fmt_13_bcl8), FULL (bncl8), FAST (bncl8) };
+static DECODE decode_bncl24 = { M32R_INSN_BNCL24, & m32r_cgen_insn_table_entries[M32R_INSN_BNCL24], EX (fmt_14_bcl24), FULL (bncl24), FAST (bncl24) };
+static DECODE decode_cmp = { M32R_INSN_CMP, & m32r_cgen_insn_table_entries[M32R_INSN_CMP], EX (fmt_17_cmp), FULL (cmp), FAST (cmp) };
+static DECODE decode_cmpi = { M32R_INSN_CMPI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPI], EX (fmt_18_cmpi), FULL (cmpi), FAST (cmpi) };
+static DECODE decode_cmpu = { M32R_INSN_CMPU, & m32r_cgen_insn_table_entries[M32R_INSN_CMPU], EX (fmt_17_cmp), FULL (cmpu), FAST (cmpu) };
+static DECODE decode_cmpui = { M32R_INSN_CMPUI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPUI], EX (fmt_19_cmpui), FULL (cmpui), FAST (cmpui) };
+static DECODE decode_cmpeq = { M32R_INSN_CMPEQ, & m32r_cgen_insn_table_entries[M32R_INSN_CMPEQ], EX (fmt_17_cmp), FULL (cmpeq), FAST (cmpeq) };
+static DECODE decode_cmpz = { M32R_INSN_CMPZ, & m32r_cgen_insn_table_entries[M32R_INSN_CMPZ], EX (fmt_20_cmpz), FULL (cmpz), FAST (cmpz) };
+static DECODE decode_div = { M32R_INSN_DIV, & m32r_cgen_insn_table_entries[M32R_INSN_DIV], EX (fmt_21_div), FULL (div), FAST (div) };
+static DECODE decode_divu = { M32R_INSN_DIVU, & m32r_cgen_insn_table_entries[M32R_INSN_DIVU], EX (fmt_21_div), FULL (divu), FAST (divu) };
+static DECODE decode_rem = { M32R_INSN_REM, & m32r_cgen_insn_table_entries[M32R_INSN_REM], EX (fmt_21_div), FULL (rem), FAST (rem) };
+static DECODE decode_remu = { M32R_INSN_REMU, & m32r_cgen_insn_table_entries[M32R_INSN_REMU], EX (fmt_21_div), FULL (remu), FAST (remu) };
+static DECODE decode_jc = { M32R_INSN_JC, & m32r_cgen_insn_table_entries[M32R_INSN_JC], EX (fmt_22_jc), FULL (jc), FAST (jc) };
+static DECODE decode_jnc = { M32R_INSN_JNC, & m32r_cgen_insn_table_entries[M32R_INSN_JNC], EX (fmt_22_jc), FULL (jnc), FAST (jnc) };
+static DECODE decode_jl = { M32R_INSN_JL, & m32r_cgen_insn_table_entries[M32R_INSN_JL], EX (fmt_23_jl), FULL (jl), FAST (jl) };
+static DECODE decode_jmp = { M32R_INSN_JMP, & m32r_cgen_insn_table_entries[M32R_INSN_JMP], EX (fmt_24_jmp), FULL (jmp), FAST (jmp) };
+static DECODE decode_ld = { M32R_INSN_LD, & m32r_cgen_insn_table_entries[M32R_INSN_LD], EX (fmt_25_ld), FULL (ld), FAST (ld) };
+static DECODE decode_ld_d = { M32R_INSN_LD_D, & m32r_cgen_insn_table_entries[M32R_INSN_LD_D], EX (fmt_26_ld_d), FULL (ld_d), FAST (ld_d) };
+static DECODE decode_ldb = { M32R_INSN_LDB, & m32r_cgen_insn_table_entries[M32R_INSN_LDB], EX (fmt_27_ldb), FULL (ldb), FAST (ldb) };
+static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDB_D], EX (fmt_28_ldb_d), FULL (ldb_d), FAST (ldb_d) };
+static DECODE decode_ldh = { M32R_INSN_LDH, & m32r_cgen_insn_table_entries[M32R_INSN_LDH], EX (fmt_29_ldh), FULL (ldh), FAST (ldh) };
+static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDH_D], EX (fmt_30_ldh_d), FULL (ldh_d), FAST (ldh_d) };
+static DECODE decode_ldub = { M32R_INSN_LDUB, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB], EX (fmt_27_ldb), FULL (ldub), FAST (ldub) };
+static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB_D], EX (fmt_28_ldb_d), FULL (ldub_d), FAST (ldub_d) };
+static DECODE decode_lduh = { M32R_INSN_LDUH, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH], EX (fmt_29_ldh), FULL (lduh), FAST (lduh) };
+static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH_D], EX (fmt_30_ldh_d), FULL (lduh_d), FAST (lduh_d) };
+static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_LD_PLUS], EX (fmt_25_ld), FULL (ld_plus), FAST (ld_plus) };
+static DECODE decode_ld24 = { M32R_INSN_LD24, & m32r_cgen_insn_table_entries[M32R_INSN_LD24], EX (fmt_31_ld24), FULL (ld24), FAST (ld24) };
+static DECODE decode_ldi8 = { M32R_INSN_LDI8, & m32r_cgen_insn_table_entries[M32R_INSN_LDI8], EX (fmt_32_ldi8), FULL (ldi8), FAST (ldi8) };
+static DECODE decode_ldi16 = { M32R_INSN_LDI16, & m32r_cgen_insn_table_entries[M32R_INSN_LDI16], EX (fmt_33_ldi16), FULL (ldi16), FAST (ldi16) };
+static DECODE decode_lock = { M32R_INSN_LOCK, & m32r_cgen_insn_table_entries[M32R_INSN_LOCK], EX (fmt_0_add), FULL (lock), FAST (lock) };
+static DECODE decode_machi_a = { M32R_INSN_MACHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MACHI_A], EX (fmt_34_machi_a), FULL (machi_a), FAST (machi_a) };
+static DECODE decode_maclo_a = { M32R_INSN_MACLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MACLO_A], EX (fmt_34_machi_a), FULL (maclo_a), FAST (maclo_a) };
+static DECODE decode_mul = { M32R_INSN_MUL, & m32r_cgen_insn_table_entries[M32R_INSN_MUL], EX (fmt_0_add), FULL (mul), FAST (mul) };
+static DECODE decode_mulhi_a = { M32R_INSN_MULHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MULHI_A], EX (fmt_35_mulhi_a), FULL (mulhi_a), FAST (mulhi_a) };
+static DECODE decode_mullo_a = { M32R_INSN_MULLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MULLO_A], EX (fmt_35_mulhi_a), FULL (mullo_a), FAST (mullo_a) };
+static DECODE decode_mv = { M32R_INSN_MV, & m32r_cgen_insn_table_entries[M32R_INSN_MV], EX (fmt_36_mv), FULL (mv), FAST (mv) };
+static DECODE decode_mvfachi_a = { M32R_INSN_MVFACHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACHI_A], EX (fmt_37_mvfachi_a), FULL (mvfachi_a), FAST (mvfachi_a) };
+static DECODE decode_mvfaclo_a = { M32R_INSN_MVFACLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACLO_A], EX (fmt_37_mvfachi_a), FULL (mvfaclo_a), FAST (mvfaclo_a) };
+static DECODE decode_mvfacmi_a = { M32R_INSN_MVFACMI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACMI_A], EX (fmt_37_mvfachi_a), FULL (mvfacmi_a), FAST (mvfacmi_a) };
+static DECODE decode_mvfc = { M32R_INSN_MVFC, & m32r_cgen_insn_table_entries[M32R_INSN_MVFC], EX (fmt_38_mvfc), FULL (mvfc), FAST (mvfc) };
+static DECODE decode_mvtachi_a = { M32R_INSN_MVTACHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACHI_A], EX (fmt_39_mvtachi_a), FULL (mvtachi_a), FAST (mvtachi_a) };
+static DECODE decode_mvtaclo_a = { M32R_INSN_MVTACLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACLO_A], EX (fmt_39_mvtachi_a), FULL (mvtaclo_a), FAST (mvtaclo_a) };
+static DECODE decode_mvtc = { M32R_INSN_MVTC, & m32r_cgen_insn_table_entries[M32R_INSN_MVTC], EX (fmt_40_mvtc), FULL (mvtc), FAST (mvtc) };
+static DECODE decode_neg = { M32R_INSN_NEG, & m32r_cgen_insn_table_entries[M32R_INSN_NEG], EX (fmt_36_mv), FULL (neg), FAST (neg) };
+static DECODE decode_nop = { M32R_INSN_NOP, & m32r_cgen_insn_table_entries[M32R_INSN_NOP], EX (fmt_41_nop), FULL (nop), FAST (nop) };
+static DECODE decode_not = { M32R_INSN_NOT, & m32r_cgen_insn_table_entries[M32R_INSN_NOT], EX (fmt_36_mv), FULL (not), FAST (not) };
+static DECODE decode_rac_a = { M32R_INSN_RAC_A, & m32r_cgen_insn_table_entries[M32R_INSN_RAC_A], EX (fmt_42_rac_a), FULL (rac_a), FAST (rac_a) };
+static DECODE decode_rach_a = { M32R_INSN_RACH_A, & m32r_cgen_insn_table_entries[M32R_INSN_RACH_A], EX (fmt_42_rac_a), FULL (rach_a), FAST (rach_a) };
+static DECODE decode_rte = { M32R_INSN_RTE, & m32r_cgen_insn_table_entries[M32R_INSN_RTE], EX (fmt_43_rte), FULL (rte), FAST (rte) };
+static DECODE decode_seth = { M32R_INSN_SETH, & m32r_cgen_insn_table_entries[M32R_INSN_SETH], EX (fmt_44_seth), FULL (seth), FAST (seth) };
+static DECODE decode_sll = { M32R_INSN_SLL, & m32r_cgen_insn_table_entries[M32R_INSN_SLL], EX (fmt_0_add), FULL (sll), FAST (sll) };
+static DECODE decode_sll3 = { M32R_INSN_SLL3, & m32r_cgen_insn_table_entries[M32R_INSN_SLL3], EX (fmt_5_addv3), FULL (sll3), FAST (sll3) };
+static DECODE decode_slli = { M32R_INSN_SLLI, & m32r_cgen_insn_table_entries[M32R_INSN_SLLI], EX (fmt_45_slli), FULL (slli), FAST (slli) };
+static DECODE decode_sra = { M32R_INSN_SRA, & m32r_cgen_insn_table_entries[M32R_INSN_SRA], EX (fmt_0_add), FULL (sra), FAST (sra) };
+static DECODE decode_sra3 = { M32R_INSN_SRA3, & m32r_cgen_insn_table_entries[M32R_INSN_SRA3], EX (fmt_5_addv3), FULL (sra3), FAST (sra3) };
+static DECODE decode_srai = { M32R_INSN_SRAI, & m32r_cgen_insn_table_entries[M32R_INSN_SRAI], EX (fmt_45_slli), FULL (srai), FAST (srai) };
+static DECODE decode_srl = { M32R_INSN_SRL, & m32r_cgen_insn_table_entries[M32R_INSN_SRL], EX (fmt_0_add), FULL (srl), FAST (srl) };
+static DECODE decode_srl3 = { M32R_INSN_SRL3, & m32r_cgen_insn_table_entries[M32R_INSN_SRL3], EX (fmt_5_addv3), FULL (srl3), FAST (srl3) };
+static DECODE decode_srli = { M32R_INSN_SRLI, & m32r_cgen_insn_table_entries[M32R_INSN_SRLI], EX (fmt_45_slli), FULL (srli), FAST (srli) };
+static DECODE decode_st = { M32R_INSN_ST, & m32r_cgen_insn_table_entries[M32R_INSN_ST], EX (fmt_17_cmp), FULL (st), FAST (st) };
+static DECODE decode_st_d = { M32R_INSN_ST_D, & m32r_cgen_insn_table_entries[M32R_INSN_ST_D], EX (fmt_46_st_d), FULL (st_d), FAST (st_d) };
+static DECODE decode_stb = { M32R_INSN_STB, & m32r_cgen_insn_table_entries[M32R_INSN_STB], EX (fmt_17_cmp), FULL (stb), FAST (stb) };
+static DECODE decode_stb_d = { M32R_INSN_STB_D, & m32r_cgen_insn_table_entries[M32R_INSN_STB_D], EX (fmt_46_st_d), FULL (stb_d), FAST (stb_d) };
+static DECODE decode_sth = { M32R_INSN_STH, & m32r_cgen_insn_table_entries[M32R_INSN_STH], EX (fmt_17_cmp), FULL (sth), FAST (sth) };
+static DECODE decode_sth_d = { M32R_INSN_STH_D, & m32r_cgen_insn_table_entries[M32R_INSN_STH_D], EX (fmt_46_st_d), FULL (sth_d), FAST (sth_d) };
+static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_PLUS], EX (fmt_17_cmp), FULL (st_plus), FAST (st_plus) };
+static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_MINUS], EX (fmt_17_cmp), FULL (st_minus), FAST (st_minus) };
+static DECODE decode_sub = { M32R_INSN_SUB, & m32r_cgen_insn_table_entries[M32R_INSN_SUB], EX (fmt_0_add), FULL (sub), FAST (sub) };
+static DECODE decode_subv = { M32R_INSN_SUBV, & m32r_cgen_insn_table_entries[M32R_INSN_SUBV], EX (fmt_0_add), FULL (subv), FAST (subv) };
+static DECODE decode_subx = { M32R_INSN_SUBX, & m32r_cgen_insn_table_entries[M32R_INSN_SUBX], EX (fmt_6_addx), FULL (subx), FAST (subx) };
+static DECODE decode_trap = { M32R_INSN_TRAP, & m32r_cgen_insn_table_entries[M32R_INSN_TRAP], EX (fmt_47_trap), FULL (trap), FAST (trap) };
+static DECODE decode_unlock = { M32R_INSN_UNLOCK, & m32r_cgen_insn_table_entries[M32R_INSN_UNLOCK], EX (fmt_17_cmp), FULL (unlock), FAST (unlock) };
+static DECODE decode_satb = { M32R_INSN_SATB, & m32r_cgen_insn_table_entries[M32R_INSN_SATB], EX (fmt_48_satb), FULL (satb), FAST (satb) };
+static DECODE decode_sath = { M32R_INSN_SATH, & m32r_cgen_insn_table_entries[M32R_INSN_SATH], EX (fmt_48_satb), FULL (sath), FAST (sath) };
+static DECODE decode_sat = { M32R_INSN_SAT, & m32r_cgen_insn_table_entries[M32R_INSN_SAT], EX (fmt_49_sat), FULL (sat), FAST (sat) };
+static DECODE decode_pcmpbz = { M32R_INSN_PCMPBZ, & m32r_cgen_insn_table_entries[M32R_INSN_PCMPBZ], EX (fmt_20_cmpz), FULL (pcmpbz), FAST (pcmpbz) };
+static DECODE decode_sadd = { M32R_INSN_SADD, & m32r_cgen_insn_table_entries[M32R_INSN_SADD], EX (fmt_50_sadd), FULL (sadd), FAST (sadd) };
+static DECODE decode_macwu1 = { M32R_INSN_MACWU1, & m32r_cgen_insn_table_entries[M32R_INSN_MACWU1], EX (fmt_51_macwu1), FULL (macwu1), FAST (macwu1) };
+static DECODE decode_msblo = { M32R_INSN_MSBLO, & m32r_cgen_insn_table_entries[M32R_INSN_MSBLO], EX (fmt_52_msblo), FULL (msblo), FAST (msblo) };
+static DECODE decode_mulwu1 = { M32R_INSN_MULWU1, & m32r_cgen_insn_table_entries[M32R_INSN_MULWU1], EX (fmt_17_cmp), FULL (mulwu1), FAST (mulwu1) };
+static DECODE decode_machl1 = { M32R_INSN_MACHL1, & m32r_cgen_insn_table_entries[M32R_INSN_MACHL1], EX (fmt_51_macwu1), FULL (machl1), FAST (machl1) };
+static DECODE decode_sc = { M32R_INSN_SC, & m32r_cgen_insn_table_entries[M32R_INSN_SC], EX (fmt_53_sc), FULL (sc), FAST (sc) };
+static DECODE decode_snc = { M32R_INSN_SNC, & m32r_cgen_insn_table_entries[M32R_INSN_SNC], EX (fmt_53_sc), FULL (snc), FAST (snc) };
+DECODE m32rx_decode_illegal = {
+  M32R_INSN_ILLEGAL, & m32r_cgen_insn_table_entries[0],
+  EX (illegal), FULL (illegal),
+  FAST (illegal)
+};
+
+/* The order must match that of `labels' in sem-switch.c.  */
+
+DECODE *m32rx_decode_vars[] = {
+  & m32rx_decode_illegal,
+  & decode_add,
+  & decode_add3,
+  & decode_and,
+  & decode_and3,
+  & decode_or,
+  & decode_or3,
+  & decode_xor,
+  & decode_xor3,
+  & decode_addi,
+  & decode_addv,
+  & decode_addv3,
+  & decode_addx,
+  & decode_bc8,
+  & decode_bc24,
+  & decode_beq,
+  & decode_beqz,
+  & decode_bgez,
+  & decode_bgtz,
+  & decode_blez,
+  & decode_bltz,
+  & decode_bnez,
+  & decode_bl8,
+  & decode_bl24,
+  & decode_bcl8,
+  & decode_bcl24,
+  & decode_bnc8,
+  & decode_bnc24,
+  & decode_bne,
+  & decode_bra8,
+  & decode_bra24,
+  & decode_bncl8,
+  & decode_bncl24,
+  & decode_cmp,
+  & decode_cmpi,
+  & decode_cmpu,
+  & decode_cmpui,
+  & decode_cmpeq,
+  & decode_cmpz,
+  & decode_div,
+  & decode_divu,
+  & decode_rem,
+  & decode_remu,
+  & decode_jc,
+  & decode_jnc,
+  & decode_jl,
+  & decode_jmp,
+  & decode_ld,
+  & decode_ld_d,
+  & decode_ldb,
+  & decode_ldb_d,
+  & decode_ldh,
+  & decode_ldh_d,
+  & decode_ldub,
+  & decode_ldub_d,
+  & decode_lduh,
+  & decode_lduh_d,
+  & decode_ld_plus,
+  & decode_ld24,
+  & decode_ldi8,
+  & decode_ldi16,
+  & decode_lock,
+  & decode_machi_a,
+  & decode_maclo_a,
+  & decode_mul,
+  & decode_mulhi_a,
+  & decode_mullo_a,
+  & decode_mv,
+  & decode_mvfachi_a,
+  & decode_mvfaclo_a,
+  & decode_mvfacmi_a,
+  & decode_mvfc,
+  & decode_mvtachi_a,
+  & decode_mvtaclo_a,
+  & decode_mvtc,
+  & decode_neg,
+  & decode_nop,
+  & decode_not,
+  & decode_rac_a,
+  & decode_rach_a,
+  & decode_rte,
+  & decode_seth,
+  & decode_sll,
+  & decode_sll3,
+  & decode_slli,
+  & decode_sra,
+  & decode_sra3,
+  & decode_srai,
+  & decode_srl,
+  & decode_srl3,
+  & decode_srli,
+  & decode_st,
+  & decode_st_d,
+  & decode_stb,
+  & decode_stb_d,
+  & decode_sth,
+  & decode_sth_d,
+  & decode_st_plus,
+  & decode_st_minus,
+  & decode_sub,
+  & decode_subv,
+  & decode_subx,
+  & decode_trap,
+  & decode_unlock,
+  & decode_satb,
+  & decode_sath,
+  & decode_sat,
+  & decode_pcmpbz,
+  & decode_sadd,
+  & decode_macwu1,
+  & decode_msblo,
+  & decode_mulwu1,
+  & decode_machl1,
+  & decode_sc,
+  & decode_snc,
+  0
+};
+
+/* The decoder needs a slightly different computed goto switch control.  */
+#ifdef __GNUC__
+#define DECODE_SWITCH(N, X) goto *labels_##N[X];
+#else
+#define DECODE_SWITCH(N, X) switch (X)
+#endif
+
+/* Given an instruction, return a pointer to its DECODE entry.  */
+
+DECODE *
+m32rx_decode (current_cpu, pc, insn)
+     SIM_CPU *current_cpu;
+     PCADDR pc;
+     insn_t insn;
+{
+  {
+#ifdef __GNUC__
+    static void *labels_0[256] = {
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && case_0_7, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && case_0_28, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && case_0_87, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && case_0_95, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && case_0_112, && case_0_113, && case_0_114, && case_0_115, 
+      && case_0_116, && case_0_117, && case_0_118, && case_0_119, 
+      && case_0_120, && case_0_121, && case_0_122, && case_0_123, 
+      && case_0_124, && case_0_125, && case_0_126, && case_0_127, 
+      && case_0_128, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && default_0, && default_0, && default_0, && default_0, 
+      && case_0_240, && case_0_241, && case_0_242, && case_0_243, 
+      && case_0_244, && case_0_245, && case_0_246, && case_0_247, 
+      && case_0_248, && case_0_249, && case_0_250, && case_0_251, 
+      && case_0_252, && case_0_253, && case_0_254, && case_0_255, 
+    };
+#endif
+    static DECODE *insns[256] = {
+      &decode_subv, &decode_subx, &decode_sub, &decode_neg, 
+      &decode_cmp, &decode_cmpu, &decode_cmpeq, 0, 
+      &decode_addv, &decode_addx, &decode_add, &decode_not, 
+      &decode_and, &decode_xor, &decode_or, &decode_illegal, 
+      &decode_srl, &decode_illegal, &decode_sra, &decode_illegal, 
+      &decode_sll, &decode_illegal, &decode_mul, &decode_illegal, 
+      &decode_mv, &decode_mvfc, &decode_mvtc, &decode_illegal, 
+      0, &decode_rte, &decode_illegal, &decode_trap, 
+      &decode_stb, &decode_illegal, &decode_sth, &decode_illegal, 
+      &decode_st, &decode_unlock, &decode_st_plus, &decode_st_minus, 
+      &decode_ldb, &decode_ldub, &decode_ldh, &decode_lduh, 
+      &decode_ld, &decode_lock, &decode_ld_plus, &decode_illegal, 
+      &decode_mulhi_a, &decode_mullo_a, &decode_illegal, &decode_illegal, 
+      &decode_machi_a, &decode_maclo_a, &decode_illegal, &decode_illegal, 
+      &decode_mulhi_a, &decode_mullo_a, &decode_illegal, &decode_illegal, 
+      &decode_machi_a, &decode_maclo_a, &decode_illegal, &decode_illegal, 
+      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
+      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
+      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
+      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
+      &decode_srli, &decode_srli, &decode_srai, &decode_srai, 
+      &decode_slli, &decode_slli, &decode_illegal, 0, 
+      &decode_rach_a, &decode_rac_a, &decode_mulwu1, &decode_macwu1, 
+      &decode_machl1, &decode_msblo, &decode_sadd, 0, 
+      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
+      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
+      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
+      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+      0, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal, 
+      &decode_addv3, &decode_illegal, &decode_add3, &decode_illegal, 
+      &decode_and3, &decode_xor3, &decode_or3, &decode_illegal, 
+      &decode_div, &decode_divu, &decode_rem, &decode_remu, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal, 
+      &decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16, 
+      &decode_stb_d, &decode_illegal, &decode_sth_d, &decode_illegal, 
+      &decode_st_d, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_ldb_d, &decode_ldub_d, &decode_ldh_d, &decode_lduh_d, 
+      &decode_ld_d, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_beq, &decode_bne, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_beqz, &decode_bnez, &decode_bltz, &decode_bgez, 
+      &decode_blez, &decode_bgtz, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_seth, &decode_illegal, &decode_illegal, &decode_illegal, 
+      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
+      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
+      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
+      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+      0, 0, 0, 0, 
+    };
+    unsigned int val;
+    val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
+    DECODE_SWITCH (0, val)
+      {
+      CASE (0, 7) :
+        {
+          static DECODE *insns[16] = {
+            &decode_cmpz, &decode_illegal, &decode_illegal, &decode_pcmpbz, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+          };
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          return insns[val];
+        }
+      CASE (0, 28) :
+        {
+          static DECODE *insns[16] = {
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_jc, &decode_jnc, &decode_jl, &decode_jmp, 
+          };
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          return insns[val];
+        }
+      CASE (0, 87) :
+        {
+          static DECODE *insns[4] = {
+            &decode_mvtachi_a, &decode_mvtaclo_a, &decode_illegal, &decode_illegal, 
+          };
+          unsigned int val = (((insn >> 0) & (3 << 0)));
+          return insns[val];
+        }
+      CASE (0, 95) :
+        {
+          static DECODE *insns[4] = {
+            &decode_mvfachi_a, &decode_mvfaclo_a, &decode_mvfacmi_a, &decode_illegal, 
+          };
+          unsigned int val = (((insn >> 0) & (3 << 0)));
+          return insns[val];
+        }
+      CASE (0, 112) :
+        {
+          static DECODE *insns[16] = {
+            &decode_nop, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_sc, &decode_snc, &decode_illegal, &decode_illegal, 
+            &decode_bcl8, &decode_bncl8, &decode_illegal, &decode_illegal, 
+            &decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8, 
+          };
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          return insns[val];
+        }
+      CASE (0, 113) : /* fall through */
+      CASE (0, 114) : /* fall through */
+      CASE (0, 115) : /* fall through */
+      CASE (0, 116) : /* fall through */
+      CASE (0, 117) : /* fall through */
+      CASE (0, 118) : /* fall through */
+      CASE (0, 119) : /* fall through */
+      CASE (0, 120) : /* fall through */
+      CASE (0, 121) : /* fall through */
+      CASE (0, 122) : /* fall through */
+      CASE (0, 123) : /* fall through */
+      CASE (0, 124) : /* fall through */
+      CASE (0, 125) : /* fall through */
+      CASE (0, 126) : /* fall through */
+      CASE (0, 127) :
+        {
+          static DECODE *insns[16] = {
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_bcl8, &decode_bncl8, &decode_illegal, &decode_illegal, 
+            &decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8, 
+          };
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          return insns[val];
+        }
+      CASE (0, 128) :
+        {
+#ifdef __GNUC__
+          static void *labels_0_128[16] = {
+            && case_0_128_0, && default_0_128, && default_0_128, && default_0_128, 
+            && default_0_128, && default_0_128, && default_0_128, && default_0_128, 
+            && default_0_128, && default_0_128, && default_0_128, && default_0_128, 
+            && default_0_128, && default_0_128, && default_0_128, && default_0_128, 
+          };
+#endif
+          static DECODE *insns[16] = {
+            0, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+          };
+          unsigned int val;
+          /* Must fetch more bits.  */
+          insn = GETIMEMUHI (current_cpu, CPU (h_pc) + 2);
+          val = (((insn >> 12) & (15 << 0)));
+          DECODE_SWITCH (0_128, val)
+            {
+            CASE (0_128, 0) :
+              {
+                static DECODE *insns[16] = {
+                  &decode_sat, &decode_satb, &decode_sath, &decode_illegal, 
+                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                };
+                unsigned int val = (((insn >> 8) & (15 << 0)));
+                return insns[val];
+              }
+            DEFAULT (0_128) : return insns[val];
+            }
+          ENDSWITCH (0_128)
+        }
+      CASE (0, 240) : /* fall through */
+      CASE (0, 241) : /* fall through */
+      CASE (0, 242) : /* fall through */
+      CASE (0, 243) : /* fall through */
+      CASE (0, 244) : /* fall through */
+      CASE (0, 245) : /* fall through */
+      CASE (0, 246) : /* fall through */
+      CASE (0, 247) : /* fall through */
+      CASE (0, 248) : /* fall through */
+      CASE (0, 249) : /* fall through */
+      CASE (0, 250) : /* fall through */
+      CASE (0, 251) : /* fall through */
+      CASE (0, 252) : /* fall through */
+      CASE (0, 253) : /* fall through */
+      CASE (0, 254) : /* fall through */
+      CASE (0, 255) :
+        {
+          static DECODE *insns[16] = {
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_bcl24, &decode_bncl24, &decode_illegal, &decode_illegal, 
+            &decode_bc24, &decode_bnc24, &decode_bl24, &decode_bra24, 
+          };
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          return insns[val];
+        }
+      DEFAULT (0) : return insns[val];
+      }
+    ENDSWITCH (0)
+  }
+}
diff --git a/sim/m32r/extract.c b/sim/m32r/extract.c
index 927e28c..e3c4b55 100644
--- a/sim/m32r/extract.c
+++ b/sim/m32r/extract.c
@@ -1,5 +1,7 @@
 /* Simulator instruction extractor for m32r.
 
+This file is machine generated with CGEN.
+
 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of the GNU Simulators.
@@ -320,6 +322,14 @@ EX_FN_NAME (m32r,fmt_11_bl8) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGB
 
   abuf->length = length;
   abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << 14);
+    }
+#endif
 #undef FLD
 }
 
@@ -337,6 +347,14 @@ EX_FN_NAME (m32r,fmt_12_bl24) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARG
 
   abuf->length = length;
   abuf->addr = pc;
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      abuf->h_gr_set = 0 | (1 << 14);
+    }
+#endif
 #undef FLD
 }
 
@@ -499,6 +517,7 @@ EX_FN_NAME (m32r,fmt_19_jl) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBU
   if (PROFILE_MODEL_P (current_cpu))
     {
       abuf->h_gr_get = 0 | (1 << f_r2);
+      abuf->h_gr_set = 0 | (1 << 14);
     }
 #endif
 #undef FLD
@@ -960,17 +979,33 @@ EX_FN_NAME (m32r,fmt_37_rac) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGB
 }
 
 void
-EX_FN_NAME (m32r,fmt_38_seth) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+EX_FN_NAME (m32r,fmt_38_rte) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+{
+#define FLD(f) abuf->fields.fmt_38_rte.f
+  EXTRACT_FMT_38_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_38_RTE_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_38_rte", (char *) 0));
+
+  abuf->length = length;
+  abuf->addr = pc;
+#undef FLD
+}
+
+void
+EX_FN_NAME (m32r,fmt_39_seth) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
 {
-#define FLD(f) abuf->fields.fmt_38_seth.f
-  EXTRACT_FMT_38_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
+#define FLD(f) abuf->fields.fmt_39_seth.f
+  EXTRACT_FMT_39_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
 
-  EXTRACT_FMT_38_SETH_CODE
+  EXTRACT_FMT_39_SETH_CODE
 
   /* Record the fields for the semantic handler.  */
   FLD (f_r1) = & CPU (h_gr)[f_r1];
   FLD (f_hi16) = f_hi16;
-  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_38_seth", "dr 0x%x", 'x', f_r1, "hi16 0x%x", 'x', f_hi16, (char *) 0));
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_39_seth", "dr 0x%x", 'x', f_r1, "hi16 0x%x", 'x', f_hi16, (char *) 0));
 
   abuf->length = length;
   abuf->addr = pc;
@@ -986,17 +1021,17 @@ EX_FN_NAME (m32r,fmt_38_seth) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARG
 }
 
 void
-EX_FN_NAME (m32r,fmt_39_slli) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+EX_FN_NAME (m32r,fmt_40_slli) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
 {
-#define FLD(f) abuf->fields.fmt_39_slli.f
-  EXTRACT_FMT_39_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+#define FLD(f) abuf->fields.fmt_40_slli.f
+  EXTRACT_FMT_40_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
 
-  EXTRACT_FMT_39_SLLI_CODE
+  EXTRACT_FMT_40_SLLI_CODE
 
   /* Record the fields for the semantic handler.  */
   FLD (f_r1) = & CPU (h_gr)[f_r1];
   FLD (f_uimm5) = f_uimm5;
-  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_39_slli", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0));
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_40_slli", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0));
 
   abuf->length = length;
   abuf->addr = pc;
@@ -1013,18 +1048,18 @@ EX_FN_NAME (m32r,fmt_39_slli) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARG
 }
 
 void
-EX_FN_NAME (m32r,fmt_40_st_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+EX_FN_NAME (m32r,fmt_41_st_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
 {
-#define FLD(f) abuf->fields.fmt_40_st_d.f
-  EXTRACT_FMT_40_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.fmt_41_st_d.f
+  EXTRACT_FMT_41_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 
-  EXTRACT_FMT_40_ST_D_CODE
+  EXTRACT_FMT_41_ST_D_CODE
 
   /* Record the fields for the semantic handler.  */
   FLD (f_r1) = & CPU (h_gr)[f_r1];
   FLD (f_r2) = & CPU (h_gr)[f_r2];
   FLD (f_simm16) = f_simm16;
-  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_40_st_d", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_41_st_d", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
 
   abuf->length = length;
   abuf->addr = pc;
@@ -1040,16 +1075,16 @@ EX_FN_NAME (m32r,fmt_40_st_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARG
 }
 
 void
-EX_FN_NAME (m32r,fmt_41_trap) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
+EX_FN_NAME (m32r,fmt_42_trap) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
 {
-#define FLD(f) abuf->fields.fmt_41_trap.f
-  EXTRACT_FMT_41_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
+#define FLD(f) abuf->fields.fmt_42_trap.f
+  EXTRACT_FMT_42_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
 
-  EXTRACT_FMT_41_TRAP_CODE
+  EXTRACT_FMT_42_TRAP_CODE
 
   /* Record the fields for the semantic handler.  */
   FLD (f_uimm4) = f_uimm4;
-  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_41_trap", "uimm4 0x%x", 'x', f_uimm4, (char *) 0));
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_42_trap", "uimm4 0x%x", 'x', f_uimm4, (char *) 0));
 
   abuf->length = length;
   abuf->addr = pc;
diff --git a/sim/m32r/m32rx.c b/sim/m32r/m32rx.c
new file mode 100644
index 0000000..1710428
--- /dev/null
+++ b/sim/m32r/m32rx.c
@@ -0,0 +1,112 @@
+/* m32rx simulator support code
+   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
+   Contributed by Cygnus Support.
+
+This file is part of GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU
+#define WANT_CPU_M32RX
+
+#include "sim-main.h"
+#include <signal.h>
+#include "libiberty.h"
+#include "bfd.h"
+/* FIXME: need to provide general mechanism for accessing target files 
+   these.  For now this is a hack to avoid getting the host version.  */
+#include "../../libgloss/m32r/sys/syscall.h"
+#include "targ-vals.h"
+
+/* The contents of BUF are in target byte order.  */
+
+void
+m32rx_fetch_register (sd, rn, buf)
+     SIM_DESC sd;
+     int rn;
+     unsigned char *buf;
+{
+  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+
+  if (rn < 16)
+    SETTWI (buf, GET_H_GR (rn));
+  else if (rn < 21)
+    SETTWI (buf, GET_H_CR (rn - 16));
+  else switch (rn) {
+    case PC_REGNUM:
+      SETTWI (buf, GET_H_PC ());
+      break;
+    case ACCL_REGNUM:
+      SETTWI (buf, GETLODI (GET_H_ACCUM ()));
+      break;
+    case ACCH_REGNUM:
+      SETTWI (buf, GETHIDI (GET_H_ACCUM ()));
+      break;
+#if 0
+    case 23: *reg = STATE_CPU_CPU (sd, 0)->h_cond;		break;
+    case 24: *reg = STATE_CPU_CPU (sd, 0)->h_sm;		break;
+    case 25: *reg = STATE_CPU_CPU (sd, 0)->h_bsm;		break;
+    case 26: *reg = STATE_CPU_CPU (sd, 0)->h_ie;		break;
+    case 27: *reg = STATE_CPU_CPU (sd, 0)->h_bie;		break;
+    case 28: *reg = STATE_CPU_CPU (sd, 0)->h_bcarry;		break; /* rename: bc */
+    case 29: memcpy (buf, &STATE_CPU_CPU (sd, 0)->h_bpc, sizeof(WI));	break; /* duplicate */
+#endif
+    default: abort ();
+  }
+}
+ 
+/* The contents of BUF are in target byte order.  */
+
+void
+m32rx_store_register (sd, rn, buf)
+     SIM_DESC sd;
+     int rn;
+     unsigned char *buf;
+{
+  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+
+  if (rn < 16)
+    SET_H_GR (rn, GETTWI (buf));
+  else if (rn < 21)
+    SET_H_CR (rn - 16, GETTWI (buf));
+  else switch (rn) {
+    case PC_REGNUM:
+      SET_H_PC (GETTWI (buf));
+      break;
+    case ACCL_REGNUM:
+      SETLODI (CPU (h_accum), GETTWI (buf));
+      break;
+    case ACCH_REGNUM:
+      SETHIDI (CPU (h_accum), GETTWI (buf));
+      break;
+#if 0
+    case 23: STATE_CPU_CPU (sd, 0)->h_cond   = *reg;			break;
+    case 24: STATE_CPU_CPU (sd, 0)->h_sm     = *reg;			break;
+    case 25: STATE_CPU_CPU (sd, 0)->h_bsm    = *reg;			break;
+    case 26: STATE_CPU_CPU (sd, 0)->h_ie     = *reg;			break;
+    case 27: STATE_CPU_CPU (sd, 0)->h_bie    = *reg;			break;
+    case 28: STATE_CPU_CPU (sd, 0)->h_bcarry = *reg;			break; /* rename: bc */
+    case 29: memcpy (&STATE_CPU_CPU (sd, 0)->h_bpc, buf, sizeof(DI));	break; /* duplicate */
+#endif
+  }
+}
+
+/* Cover fn to access h-accums.  */
+
+UDI
+m32rx_h_accums_get (SIM_CPU *current_cpu, UINT accum)
+{
+  return 0;
+}
diff --git a/sim/m32r/mloopx.in b/sim/m32r/mloopx.in
new file mode 100644
index 0000000..533aca5
--- /dev/null
+++ b/sim/m32r/mloopx.in
@@ -0,0 +1,133 @@
+# Simulator main loop for m32rx. -*- C -*-
+# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in init|support|{full,fast}-{extract,exec}-{scache,noscache}
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+EOF
+
+;;
+
+xinit)
+
+cat <<EOF
+  USI insn,insn1,insn2;
+  DECODE *decode,*d1,*d2;
+  int icount,icount2;
+  ARGBUF abufs[MAX_PARALLEL_INSNS];
+  SEM_ARG sem_arg;
+
+EOF
+
+;;
+
+xfull-extract-* | xfast-extract-*)
+
+cat <<EOF
+{
+  PCADDR pc = CPU (h_pc);
+
+  if ((pc & 3) != 0)
+    {
+      insn1 = GETIMEMUHI (current_cpu, pc);
+      insn1 &= 0x7fff;
+      d1 = m32rx_decode (current_cpu, pc, insn1);
+      icount = 1;
+    }
+  else
+    {
+      insn1 = GETIMEMUSI (current_cpu, pc);
+      if ((SI) insn1 < 0)
+	{
+	  d1 = m32rx_decode (current_cpu, pc, insn1 >> 16);
+	  icount = 1;
+	}
+      else
+	{
+	  if (insn & 0x8000)
+	    {
+	      insn2 = insn1 & 0x7fff;
+	      insn1 = insn1 >> 16;
+	      d1 = m32rx_decode (current_cpu, pc, insn1);
+	      d2 = m32rx_decode (current_cpu, pc, insn2);
+	      icount = 2;
+	    }
+	  else
+	    {
+	      insn1 = insn1 >> 16;
+	      d1 = m32rx_decode (current_cpu, pc, insn1);
+	      icount = 1;
+	    }
+	}
+    }
+
+  icount2 = icount;
+  insn = insn1;
+  decode = d1;
+  do
+    {
+#define DEFINE_SWITCH
+#include "readx.c"
+
+      insn = insn2;
+      decode = d2;
+    }
+  while (--icount2 > 0);
+}
+EOF
+
+;;
+
+xfull-exec-* | xfast-exec-*)
+
+cat <<EOF
+{
+  decode = d1;
+  do
+    {
+      PCADDR new_pc;
+      TRACE_INSN_INIT (current_cpu);
+      TRACE_INSN (current_cpu, sc->argbuf.opcode, (const struct argbuf *) &sc->argbuf, sc->argbuf.addr);
+      new_pc = (*decode->semantic) (current_cpu, &sc->argbuf);
+      TRACE_INSN_FINI (current_cpu);
+      PROFILE_COUNT_INSN (current_cpu, pc, CGEN_INSN_INDEX (sc->argbuf.opcode));
+      CPU (h_pc) = new_pc;
+      decode = d2;
+    }
+  while (--icount > 0);
+}
+EOF
+
+;;
+
+*)
+  echo "Invalid argument to mainloop.in: $1" >&2
+  exit 1
+  ;;
+
+esac
diff --git a/sim/m32r/readx.c b/sim/m32r/readx.c
index 3b79638..26775a3 100644
--- a/sim/m32r/readx.c
+++ b/sim/m32r/readx.c
@@ -1,5 +1,7 @@
 /* Simulator instruction operand reader for m32r.
 
+This file is machine generated with CGEN.
+
 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of the GNU Simulators.
@@ -29,7 +31,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifdef DEFINE_LABELS
 #undef DEFINE_LABELS
 
-
   /* The labels have the case they have because the enum of insn types
      is all uppercase and in the non-stdc case the fmt symbol is built
      into the enum name.
@@ -72,28 +73,26 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     && case_read_READ_FMT_31_LD24,
     && case_read_READ_FMT_32_LDI8,
     && case_read_READ_FMT_33_LDI16,
-    && case_read_READ_FMT_34_MACHI,
-    && case_read_READ_FMT_35_MACHI_A,
-    && case_read_READ_FMT_36_MULHI_A,
-    && case_read_READ_FMT_37_MV,
-    && case_read_READ_FMT_38_MVFACHI,
-    && case_read_READ_FMT_39_MVFACHI_A,
-    && case_read_READ_FMT_40_MVFC,
-    && case_read_READ_FMT_41_MVTACHI,
-    && case_read_READ_FMT_42_MVTACHI_A,
-    && case_read_READ_FMT_43_MVTC,
-    && case_read_READ_FMT_44_NOP,
-    && case_read_READ_FMT_45_RAC,
-    && case_read_READ_FMT_46_RAC_A,
-    && case_read_READ_FMT_47_SETH,
-    && case_read_READ_FMT_48_SLLI,
-    && case_read_READ_FMT_49_ST_D,
-    && case_read_READ_FMT_50_TRAP,
-    && case_read_READ_FMT_51_SATB,
-    && case_read_READ_FMT_52_PCMPBZ,
-    && case_read_READ_FMT_53_SADD,
-    && case_read_READ_FMT_54_MACWU1,
-    && case_read_READ_FMT_55_SC,
+    && case_read_READ_FMT_34_MACHI_A,
+    && case_read_READ_FMT_35_MULHI_A,
+    && case_read_READ_FMT_36_MV,
+    && case_read_READ_FMT_37_MVFACHI_A,
+    && case_read_READ_FMT_38_MVFC,
+    && case_read_READ_FMT_39_MVTACHI_A,
+    && case_read_READ_FMT_40_MVTC,
+    && case_read_READ_FMT_41_NOP,
+    && case_read_READ_FMT_42_RAC_A,
+    && case_read_READ_FMT_43_RTE,
+    && case_read_READ_FMT_44_SETH,
+    && case_read_READ_FMT_45_SLLI,
+    && case_read_READ_FMT_46_ST_D,
+    && case_read_READ_FMT_47_TRAP,
+    && case_read_READ_FMT_48_SATB,
+    && case_read_READ_FMT_49_SAT,
+    && case_read_READ_FMT_50_SADD,
+    && case_read_READ_FMT_51_MACWU1,
+    && case_read_READ_FMT_52_MSBLO,
+    && case_read_READ_FMT_53_SC,
     0
   };
   extern DECODE *m32rx_decode_vars[];
@@ -121,7 +120,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
   EXTRACT_FMT_0_ADD_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -135,7 +133,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_1_add3.f
   EXTRACT_FMT_1_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
   EXTRACT_FMT_1_ADD3_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -149,7 +146,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_2_and3.f
   EXTRACT_FMT_2_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-
   EXTRACT_FMT_2_AND3_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -163,7 +159,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_3_or3.f
   EXTRACT_FMT_3_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-
   EXTRACT_FMT_3_OR3_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -177,7 +172,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_4_addi.f
   EXTRACT_FMT_4_ADDI_VARS /* f-op1 f-r1 f-simm8 */
-
   EXTRACT_FMT_4_ADDI_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -191,7 +185,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
   EXTRACT_FMT_5_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
   EXTRACT_FMT_5_ADDV3_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -205,7 +198,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_6_addx.f
   EXTRACT_FMT_6_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
   EXTRACT_FMT_6_ADDX_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -220,7 +212,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_7_bc8.f
   EXTRACT_FMT_7_BC8_VARS /* f-op1 f-r1 f-disp8 */
-
   EXTRACT_FMT_7_BC8_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -234,7 +225,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_8_bc24.f
   EXTRACT_FMT_8_BC24_VARS /* f-op1 f-r1 f-disp24 */
-
   EXTRACT_FMT_8_BC24_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -248,7 +238,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_9_beq.f
   EXTRACT_FMT_9_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
-
   EXTRACT_FMT_9_BEQ_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -263,7 +252,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
   EXTRACT_FMT_10_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
-
   EXTRACT_FMT_10_BEQZ_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -277,7 +265,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_11_bl8.f
   EXTRACT_FMT_11_BL8_VARS /* f-op1 f-r1 f-disp8 */
-
   EXTRACT_FMT_11_BL8_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -291,7 +278,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_12_bl24.f
   EXTRACT_FMT_12_BL24_VARS /* f-op1 f-r1 f-disp24 */
-
   EXTRACT_FMT_12_BL24_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -305,7 +291,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_13_bcl8.f
   EXTRACT_FMT_13_BCL8_VARS /* f-op1 f-r1 f-disp8 */
-
   EXTRACT_FMT_13_BCL8_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -320,7 +305,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_14_bcl24.f
   EXTRACT_FMT_14_BCL24_VARS /* f-op1 f-r1 f-disp24 */
-
   EXTRACT_FMT_14_BCL24_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -335,7 +319,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_15_bra8.f
   EXTRACT_FMT_15_BRA8_VARS /* f-op1 f-r1 f-disp8 */
-
   EXTRACT_FMT_15_BRA8_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -348,7 +331,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_16_bra24.f
   EXTRACT_FMT_16_BRA24_VARS /* f-op1 f-r1 f-disp24 */
-
   EXTRACT_FMT_16_BRA24_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -361,7 +343,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
   EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
   EXTRACT_FMT_17_CMP_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -375,7 +356,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_18_cmpi.f
   EXTRACT_FMT_18_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
   EXTRACT_FMT_18_CMPI_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -389,7 +369,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_19_cmpui.f
   EXTRACT_FMT_19_CMPUI_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-
   EXTRACT_FMT_19_CMPUI_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -403,7 +382,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_20_cmpz.f
   EXTRACT_FMT_20_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
   EXTRACT_FMT_20_CMPZ_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -416,7 +394,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
   EXTRACT_FMT_21_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
   EXTRACT_FMT_21_DIV_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -430,7 +407,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_22_jc.f
   EXTRACT_FMT_22_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
   EXTRACT_FMT_22_JC_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -444,7 +420,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_23_jl.f
   EXTRACT_FMT_23_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
   EXTRACT_FMT_23_JL_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -458,7 +433,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_24_jmp.f
   EXTRACT_FMT_24_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
   EXTRACT_FMT_24_JMP_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -471,11 +445,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_25_ld.f
   EXTRACT_FMT_25_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
   EXTRACT_FMT_25_LD_CODE
 
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (h_memory) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
+      OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
       OPRND (sr) = CPU (h_gr[f_r2]);
 #undef OPRND
     }
@@ -485,11 +458,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_26_ld_d.f
   EXTRACT_FMT_26_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
   EXTRACT_FMT_26_LD_D_CODE
 
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (h_memory) = GETMEMSI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
+      OPRND (h_memory_add_WI_sr_slo16) = GETMEMSI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
       OPRND (slo16) = f_simm16;
       OPRND (sr) = CPU (h_gr[f_r2]);
 #undef OPRND
@@ -500,11 +472,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_27_ldb.f
   EXTRACT_FMT_27_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
   EXTRACT_FMT_27_LDB_CODE
 
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (h_memory) = GETMEMQI (current_cpu, CPU (h_gr[f_r2]));
+      OPRND (h_memory_sr) = GETMEMQI (current_cpu, CPU (h_gr[f_r2]));
       OPRND (sr) = CPU (h_gr[f_r2]);
 #undef OPRND
     }
@@ -514,11 +485,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_28_ldb_d.f
   EXTRACT_FMT_28_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
   EXTRACT_FMT_28_LDB_D_CODE
 
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (h_memory) = GETMEMQI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
+      OPRND (h_memory_add_WI_sr_slo16) = GETMEMQI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
       OPRND (slo16) = f_simm16;
       OPRND (sr) = CPU (h_gr[f_r2]);
 #undef OPRND
@@ -529,11 +499,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_29_ldh.f
   EXTRACT_FMT_29_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
   EXTRACT_FMT_29_LDH_CODE
 
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (h_memory) = GETMEMHI (current_cpu, CPU (h_gr[f_r2]));
+      OPRND (h_memory_sr) = GETMEMHI (current_cpu, CPU (h_gr[f_r2]));
       OPRND (sr) = CPU (h_gr[f_r2]);
 #undef OPRND
     }
@@ -543,11 +512,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_30_ldh_d.f
   EXTRACT_FMT_30_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
   EXTRACT_FMT_30_LDH_D_CODE
 
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (h_memory) = GETMEMHI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
+      OPRND (h_memory_add_WI_sr_slo16) = GETMEMHI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
       OPRND (slo16) = f_simm16;
       OPRND (sr) = CPU (h_gr[f_r2]);
 #undef OPRND
@@ -558,7 +526,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_31_ld24.f
   EXTRACT_FMT_31_LD24_VARS /* f-op1 f-r1 f-uimm24 */
-
   EXTRACT_FMT_31_LD24_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -571,7 +538,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_32_ldi8.f
   EXTRACT_FMT_32_LDI8_VARS /* f-op1 f-r1 f-simm8 */
-
   EXTRACT_FMT_32_LDI8_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -584,7 +550,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     {
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_33_ldi16.f
   EXTRACT_FMT_33_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
   EXTRACT_FMT_33_LDI16_CODE
 
       /* Fetch the input operands for the semantic handler.  */
@@ -593,27 +558,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_34_MACHI) : /* e.g. machi $src1,$src2 */
+    CASE (read, READ_FMT_34_MACHI_A) : /* e.g. machi $src1,$src2,$acc */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
-  EXTRACT_FMT_34_MACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_34_MACHI_CODE
-
-      /* Fetch the input operands for the semantic handler.  */
-      OPRND (accum) = CPU (h_accum);
-      OPRND (src1) = CPU (h_gr[f_r1]);
-      OPRND (src2) = CPU (h_gr[f_r2]);
-#undef OPRND
-    }
-    BREAK (read);
-
-    CASE (read, READ_FMT_35_MACHI_A) : /* e.g. machi $src1,$src2,$acc */
-    {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f
-  EXTRACT_FMT_35_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
-
-  EXTRACT_FMT_35_MACHI_A_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi_a.f
+  EXTRACT_FMT_34_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
+  EXTRACT_FMT_34_MACHI_A_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (acc) = m32rx_h_accums_get (current_cpu, f_acc);
@@ -623,12 +572,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_36_MULHI_A) : /* e.g. mulhi $src1,$src2,$acc */
+    CASE (read, READ_FMT_35_MULHI_A) : /* e.g. mulhi $src1,$src2,$acc */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f
-  EXTRACT_FMT_36_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
-
-  EXTRACT_FMT_36_MULHI_A_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_mulhi_a.f
+  EXTRACT_FMT_35_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
+  EXTRACT_FMT_35_MULHI_A_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (src1) = CPU (h_gr[f_r1]);
@@ -637,12 +585,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_37_MV) : /* e.g. mv $dr,$sr */
+    CASE (read, READ_FMT_36_MV) : /* e.g. mv $dr,$sr */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f
-  EXTRACT_FMT_37_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_37_MV_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mv.f
+  EXTRACT_FMT_36_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_36_MV_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (sr) = CPU (h_gr[f_r2]);
@@ -650,25 +597,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_38_MVFACHI) : /* e.g. mvfachi $dr */
+    CASE (read, READ_FMT_37_MVFACHI_A) : /* e.g. mvfachi $dr,$accs */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f
-  EXTRACT_FMT_38_MVFACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_38_MVFACHI_CODE
-
-      /* Fetch the input operands for the semantic handler.  */
-      OPRND (accum) = CPU (h_accum);
-#undef OPRND
-    }
-    BREAK (read);
-
-    CASE (read, READ_FMT_39_MVFACHI_A) : /* e.g. mvfachi $dr,$accs */
-    {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f
-  EXTRACT_FMT_39_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
-
-  EXTRACT_FMT_39_MVFACHI_A_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mvfachi_a.f
+  EXTRACT_FMT_37_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+  EXTRACT_FMT_37_MVFACHI_A_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
@@ -676,12 +609,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_40_MVFC) : /* e.g. mvfc $dr,$scr */
+    CASE (read, READ_FMT_38_MVFC) : /* e.g. mvfc $dr,$scr */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_40_mvfc.f
-  EXTRACT_FMT_40_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_40_MVFC_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfc.f
+  EXTRACT_FMT_38_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_38_MVFC_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (scr) = m32rx_h_cr_get (current_cpu, f_r2);
@@ -689,26 +621,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_41_MVTACHI) : /* e.g. mvtachi $src1 */
+    CASE (read, READ_FMT_39_MVTACHI_A) : /* e.g. mvtachi $src1,$accs */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_mvtachi.f
-  EXTRACT_FMT_41_MVTACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_41_MVTACHI_CODE
-
-      /* Fetch the input operands for the semantic handler.  */
-      OPRND (accum) = CPU (h_accum);
-      OPRND (src1) = CPU (h_gr[f_r1]);
-#undef OPRND
-    }
-    BREAK (read);
-
-    CASE (read, READ_FMT_42_MVTACHI_A) : /* e.g. mvtachi $src1,$accs */
-    {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_mvtachi_a.f
-  EXTRACT_FMT_42_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
-
-  EXTRACT_FMT_42_MVTACHI_A_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvtachi_a.f
+  EXTRACT_FMT_39_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+  EXTRACT_FMT_39_MVTACHI_A_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
@@ -717,12 +634,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_43_MVTC) : /* e.g. mvtc $sr,$dcr */
+    CASE (read, READ_FMT_40_MVTC) : /* e.g. mvtc $sr,$dcr */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_43_mvtc.f
-  EXTRACT_FMT_43_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_43_MVTC_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_40_mvtc.f
+  EXTRACT_FMT_40_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_40_MVTC_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (sr) = CPU (h_gr[f_r2]);
@@ -730,50 +646,49 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_44_NOP) : /* e.g. nop */
+    CASE (read, READ_FMT_41_NOP) : /* e.g. nop */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_nop.f
-  EXTRACT_FMT_44_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_44_NOP_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_nop.f
+  EXTRACT_FMT_41_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_41_NOP_CODE
 
       /* Fetch the input operands for the semantic handler.  */
 #undef OPRND
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_45_RAC) : /* e.g. rac */
+    CASE (read, READ_FMT_42_RAC_A) : /* e.g. rac $accs */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_rac.f
-  EXTRACT_FMT_45_RAC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_45_RAC_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_rac_a.f
+  EXTRACT_FMT_42_RAC_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+  EXTRACT_FMT_42_RAC_A_CODE
 
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (accum) = CPU (h_accum);
+      OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
 #undef OPRND
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_46_RAC_A) : /* e.g. rac $accs */
+    CASE (read, READ_FMT_43_RTE) : /* e.g. rte */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_rac_a.f
-  EXTRACT_FMT_46_RAC_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
-
-  EXTRACT_FMT_46_RAC_A_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_43_rte.f
+  EXTRACT_FMT_43_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_43_RTE_CODE
 
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
+      OPRND (h_bcond_0) = CPU (h_bcond);
+      OPRND (h_bie_0) = CPU (h_bie);
+      OPRND (h_bpc_0) = CPU (h_bpc);
+      OPRND (h_bsm_0) = CPU (h_bsm);
 #undef OPRND
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_47_SETH) : /* e.g. seth $dr,$hi16 */
+    CASE (read, READ_FMT_44_SETH) : /* e.g. seth $dr,#$hi16 */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_47_seth.f
-  EXTRACT_FMT_47_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
-
-  EXTRACT_FMT_47_SETH_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_seth.f
+  EXTRACT_FMT_44_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
+  EXTRACT_FMT_44_SETH_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (hi16) = f_hi16;
@@ -781,12 +696,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_48_SLLI) : /* e.g. slli $dr,#$uimm5 */
+    CASE (read, READ_FMT_45_SLLI) : /* e.g. slli $dr,#$uimm5 */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f
-  EXTRACT_FMT_48_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
-
-  EXTRACT_FMT_48_SLLI_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_slli.f
+  EXTRACT_FMT_45_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+  EXTRACT_FMT_45_SLLI_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (dr) = CPU (h_gr[f_r1]);
@@ -795,12 +709,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_49_ST_D) : /* e.g. st $src1,@($slo16,$src2) */
+    CASE (read, READ_FMT_46_ST_D) : /* e.g. st $src1,@($slo16,$src2) */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f
-  EXTRACT_FMT_49_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_49_ST_D_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_st_d.f
+  EXTRACT_FMT_46_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_46_ST_D_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (slo16) = f_simm16;
@@ -810,12 +723,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_50_TRAP) : /* e.g. trap #$uimm4 */
+    CASE (read, READ_FMT_47_TRAP) : /* e.g. trap #$uimm4 */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_50_trap.f
-  EXTRACT_FMT_50_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
-
-  EXTRACT_FMT_50_TRAP_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_47_trap.f
+  EXTRACT_FMT_47_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
+  EXTRACT_FMT_47_TRAP_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (uimm4) = f_uimm4;
@@ -823,65 +735,77 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_51_SATB) : /* e.g. satb $dr,$src2 */
+    CASE (read, READ_FMT_48_SATB) : /* e.g. satb $dr,$src2 */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f
-  EXTRACT_FMT_51_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-
-  EXTRACT_FMT_51_SATB_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_satb.f
+  EXTRACT_FMT_48_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_48_SATB_CODE
 
       /* Fetch the input operands for the semantic handler.  */
+      OPRND (src2) = CPU (h_gr[f_r2]);
 #undef OPRND
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_52_PCMPBZ) : /* e.g. pcmpbz $src2 */
+    CASE (read, READ_FMT_49_SAT) : /* e.g. sat $dr,$src2 */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_52_pcmpbz.f
-  EXTRACT_FMT_52_PCMPBZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_52_PCMPBZ_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_sat.f
+  EXTRACT_FMT_49_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_49_SAT_CODE
 
       /* Fetch the input operands for the semantic handler.  */
+      OPRND (condbit) = CPU (h_cond);
+      OPRND (src2) = CPU (h_gr[f_r2]);
 #undef OPRND
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_53_SADD) : /* e.g. sadd */
+    CASE (read, READ_FMT_50_SADD) : /* e.g. sadd */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_53_sadd.f
-  EXTRACT_FMT_53_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_53_SADD_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_50_sadd.f
+  EXTRACT_FMT_50_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_50_SADD_CODE
 
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (h_accums) = m32rx_h_accums_get (current_cpu, 0);
-      OPRND (h_accums) = m32rx_h_accums_get (current_cpu, 1);
+      OPRND (h_accums_0) = m32rx_h_accums_get (current_cpu, 0);
+      OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, 1);
 #undef OPRND
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_54_MACWU1) : /* e.g. macwu1 $src1,$src2 */
+    CASE (read, READ_FMT_51_MACWU1) : /* e.g. macwu1 $src1,$src2 */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_54_macwu1.f
-  EXTRACT_FMT_54_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_54_MACWU1_CODE
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_macwu1.f
+  EXTRACT_FMT_51_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_51_MACWU1_CODE
 
       /* Fetch the input operands for the semantic handler.  */
-      OPRND (h_accums) = m32rx_h_accums_get (current_cpu, 1);
+      OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, 1);
       OPRND (src1) = CPU (h_gr[f_r1]);
       OPRND (src2) = CPU (h_gr[f_r2]);
 #undef OPRND
     }
     BREAK (read);
 
-    CASE (read, READ_FMT_55_SC) : /* e.g. sc */
+    CASE (read, READ_FMT_52_MSBLO) : /* e.g. msblo $src1,$src2 */
     {
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_55_sc.f
-  EXTRACT_FMT_55_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_52_msblo.f
+  EXTRACT_FMT_52_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_52_MSBLO_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (accum) = CPU (h_accum);
+      OPRND (src1) = CPU (h_gr[f_r1]);
+      OPRND (src2) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
 
-  EXTRACT_FMT_55_SC_CODE
+    CASE (read, READ_FMT_53_SC) : /* e.g. sc */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_53_sc.f
+  EXTRACT_FMT_53_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_53_SC_CODE
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (condbit) = CPU (h_cond);
diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c
index 1bee915..3e5d4db 100644
--- a/sim/m32r/sem.c
+++ b/sim/m32r/sem.c
@@ -1,5 +1,7 @@
 /* Simulator instruction semantics for m32r.
 
+This file is machine generated with CGEN.
+
 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of the GNU Simulators.
@@ -40,37 +42,43 @@ SEM_FN_NAME (m32r,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = ADDSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform add3: add3 $dr,$sr,$slo16.  */
+/* Perform add3: add3 $dr,$sr,#$slo16.  */
 CIA
 SEM_FN_NAME (m32r,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_1_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = ADDSI (* FLD (f_r2), FLD (f_simm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -82,37 +90,43 @@ SEM_FN_NAME (m32r,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = ANDSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform and3: and3 $dr,$sr,$uimm16.  */
+/* Perform and3: and3 $dr,$sr,#$uimm16.  */
 CIA
 SEM_FN_NAME (m32r,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_2_and3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = ANDSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -124,37 +138,43 @@ SEM_FN_NAME (m32r,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = ORSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform or3: or3 $dr,$sr,$ulo16.  */
+/* Perform or3: or3 $dr,$sr,#$ulo16.  */
 CIA
 SEM_FN_NAME (m32r,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_3_or3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = ORSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -166,58 +186,67 @@ SEM_FN_NAME (m32r,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = XORSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform xor3: xor3 $dr,$sr,$uimm16.  */
+/* Perform xor3: xor3 $dr,$sr,#$uimm16.  */
 CIA
 SEM_FN_NAME (m32r,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_2_and3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = XORSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform addi: addi $dr,$simm8.  */
+/* Perform addi: addi $dr,#$simm8.  */
 CIA
 SEM_FN_NAME (m32r,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_4_addi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = ADDSI (* FLD (f_r1), FLD (f_simm8));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -229,6 +258,7 @@ SEM_FN_NAME (m32r,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do {
   BI temp1;SI temp0;
   temp0 = ADDSI (* FLD (f_r1), * FLD (f_r2));
@@ -238,25 +268,28 @@ do {
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform addv3: addv3 $dr,$sr,$simm16.  */
+/* Perform addv3: addv3 $dr,$sr,#$simm16.  */
 CIA
 SEM_FN_NAME (m32r,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do {
   BI temp1;SI temp0;
   temp0 = ADDSI (* FLD (f_r2), FLD (f_simm16));
@@ -266,14 +299,16 @@ do {
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -285,6 +320,7 @@ SEM_FN_NAME (m32r,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_6_addx.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do {
   BI temp1;SI temp0;
   temp0 = ADDCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
@@ -294,14 +330,16 @@ do {
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -314,16 +352,19 @@ SEM_FN_NAME (m32r,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (CPU (h_cond)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -336,16 +377,19 @@ SEM_FN_NAME (m32r,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (CPU (h_cond)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -358,17 +402,20 @@ SEM_FN_NAME (m32r,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (EQSI (* FLD (f_r1), * FLD (f_r2))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -381,17 +428,20 @@ SEM_FN_NAME (m32r,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (EQSI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -404,17 +454,20 @@ SEM_FN_NAME (m32r,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (GESI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -427,17 +480,20 @@ SEM_FN_NAME (m32r,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (GTSI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -450,17 +506,20 @@ SEM_FN_NAME (m32r,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (LESI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -473,17 +532,20 @@ SEM_FN_NAME (m32r,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (LTSI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -496,17 +558,20 @@ SEM_FN_NAME (m32r,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (NESI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -519,18 +584,22 @@ SEM_FN_NAME (m32r,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 do {
   CPU (h_gr[14]) = ADDSI (ANDSI (CPU (h_pc), -4), 4);
-  TRACE_RESULT (current_cpu, "h-gr", 'x', CPU (h_gr[14]));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
   taken_p = 1;
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_mark_set_h_gr (current_cpu, abuf);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -543,18 +612,22 @@ SEM_FN_NAME (m32r,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 do {
   CPU (h_gr[14]) = ADDSI (CPU (h_pc), 4);
-  TRACE_RESULT (current_cpu, "h-gr", 'x', CPU (h_gr[14]));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
   taken_p = 1;
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_mark_set_h_gr (current_cpu, abuf);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -567,16 +640,19 @@ SEM_FN_NAME (m32r,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (NOTBI (CPU (h_cond))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -589,16 +665,19 @@ SEM_FN_NAME (m32r,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (NOTBI (CPU (h_cond))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -611,17 +690,20 @@ SEM_FN_NAME (m32r,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 if (NESI (* FLD (f_r1), * FLD (f_r2))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
   taken_p = 1;
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -634,14 +716,17 @@ SEM_FN_NAME (m32r,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
   taken_p = 1;
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -654,14 +739,17 @@ SEM_FN_NAME (m32r,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
   taken_p = 1;
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -673,35 +761,41 @@ SEM_FN_NAME (m32r,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_cond) = LTSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform cmpi: cmpi $src2,$simm16.  */
+/* Perform cmpi: cmpi $src2,#$simm16.  */
 CIA
 SEM_FN_NAME (m32r,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_16_cmpi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_cond) = LTSI (* FLD (f_r2), FLD (f_simm16));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -713,35 +807,41 @@ SEM_FN_NAME (m32r,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_cond) = LTUSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform cmpui: cmpui $src2,$uimm16.  */
+/* Perform cmpui: cmpui $src2,#$uimm16.  */
 CIA
 SEM_FN_NAME (m32r,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_17_cmpui.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_cond) = LTUSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -753,18 +853,21 @@ SEM_FN_NAME (m32r,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_18_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = DIVSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -776,18 +879,21 @@ SEM_FN_NAME (m32r,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_18_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = UDIVSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -799,18 +905,21 @@ SEM_FN_NAME (m32r,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_18_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = MODSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -822,18 +931,21 @@ SEM_FN_NAME (m32r,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_18_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = UMODSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -846,22 +958,26 @@ SEM_FN_NAME (m32r,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 do {
   USI temp1;SI temp0;
   temp0 = ADDSI (ANDSI (CPU (h_pc), -4), 4);
   temp1 = * FLD (f_r2);
   CPU (h_gr[14]) = temp0;
-  TRACE_RESULT (current_cpu, "h-gr", 'x', CPU (h_gr[14]));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1));
   taken_p = 1;
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_mark_set_h_gr (current_cpu, abuf);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -874,15 +990,18 @@ SEM_FN_NAME (m32r,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, * FLD (f_r2)));
   taken_p = 1;
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -894,16 +1013,19 @@ SEM_FN_NAME (m32r,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_21_ld.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -915,16 +1037,19 @@ SEM_FN_NAME (m32r,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_22_ld_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -936,16 +1061,19 @@ SEM_FN_NAME (m32r,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_23_ldb.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -957,16 +1085,19 @@ SEM_FN_NAME (m32r,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_24_ldb_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -978,16 +1109,19 @@ SEM_FN_NAME (m32r,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_25_ldh.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -999,16 +1133,19 @@ SEM_FN_NAME (m32r,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_26_ldh_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1020,16 +1157,19 @@ SEM_FN_NAME (m32r,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_23_ldb.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1041,16 +1181,19 @@ SEM_FN_NAME (m32r,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_24_ldb_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1062,16 +1205,19 @@ SEM_FN_NAME (m32r,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_25_ldh.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1083,16 +1229,19 @@ SEM_FN_NAME (m32r,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_26_ldh_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1104,6 +1253,7 @@ SEM_FN_NAME (m32r,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_21_ld.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do {
   SI temp1;SI temp0;
   temp0 = GETMEMSI (current_cpu, * FLD (f_r2));
@@ -1113,54 +1263,62 @@ do {
 * FLD (f_r2) = temp1;
   TRACE_RESULT (current_cpu, "sr", 'x', * FLD (f_r2));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform ld24: ld24 $dr,$uimm24.  */
+/* Perform ld24: ld24 $dr,#$uimm24.  */
 CIA
 SEM_FN_NAME (m32r,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_27_ld24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = FLD (f_uimm24);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform ldi8: ldi $dr,$simm8.  */
+/* Perform ldi8: ldi $dr,#$simm8.  */
 CIA
 SEM_FN_NAME (m32r,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_28_ldi8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = FLD (f_simm8);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1172,15 +1330,18 @@ SEM_FN_NAME (m32r,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_29_ldi16.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = FLD (f_simm16);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1192,15 +1353,18 @@ SEM_FN_NAME (m32r,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1212,15 +1376,18 @@ SEM_FN_NAME (m32r,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_30_machi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1232,15 +1399,18 @@ SEM_FN_NAME (m32r,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_30_machi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1252,15 +1422,18 @@ SEM_FN_NAME (m32r,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_30_machi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1272,15 +1445,18 @@ SEM_FN_NAME (m32r,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_30_machi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1292,16 +1468,19 @@ SEM_FN_NAME (m32r,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = MULSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1313,15 +1492,18 @@ SEM_FN_NAME (m32r,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 16), 16);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1333,15 +1515,18 @@ SEM_FN_NAME (m32r,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 16), 16);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1353,15 +1538,18 @@ SEM_FN_NAME (m32r,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1373,15 +1561,18 @@ SEM_FN_NAME (m32r,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1393,16 +1584,19 @@ SEM_FN_NAME (m32r,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_31_mv.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = * FLD (f_r2);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1414,15 +1608,18 @@ SEM_FN_NAME (m32r,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 32));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1434,15 +1631,18 @@ SEM_FN_NAME (m32r,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = TRUNCDISI (CPU (h_accum));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1454,15 +1654,18 @@ SEM_FN_NAME (m32r,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1474,15 +1677,18 @@ SEM_FN_NAME (m32r,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_33_mvfc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = m32r_h_cr_get (current_cpu, FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1494,15 +1700,18 @@ SEM_FN_NAME (m32r,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_34_mvtachi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (f_r1)), 32));
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1514,15 +1723,18 @@ SEM_FN_NAME (m32r,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_34_mvtachi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
   CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0xffffffff, 0)), EXTSIDI (* FLD (f_r1)));
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1534,15 +1746,18 @@ SEM_FN_NAME (m32r,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_35_mvtc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dcr", 'x', m32r_h_cr_get (current_cpu, FLD (f_r1)));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1554,16 +1769,19 @@ SEM_FN_NAME (m32r,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_31_mv.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = NEGSI (* FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1575,13 +1793,16 @@ SEM_FN_NAME (m32r,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_36_nop.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1593,16 +1814,19 @@ SEM_FN_NAME (m32r,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_31_mv.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = INVSI (* FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1614,6 +1838,7 @@ SEM_FN_NAME (m32r,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_37_rac.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do {
   DI tmp_tmp1;
   tmp_tmp1 = ANDDI (CPU (h_accum), MAKEDI (16777215, 0xffffffff));
@@ -1630,12 +1855,14 @@ if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760
   CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1647,6 +1874,7 @@ SEM_FN_NAME (m32r,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_37_rac.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do {
   DI tmp_tmp1;
   tmp_tmp1 = ANDDI (CPU (h_accum), MAKEDI (16777215, 0xffffffff));
@@ -1663,12 +1891,14 @@ if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760
   CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1677,47 +1907,53 @@ if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760
 CIA
 SEM_FN_NAME (m32r,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_36_nop.f
+#define FLD(f) abuf->fields.fmt_38_rte.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 do {
   CPU (h_sm) = CPU (h_bsm);
-  TRACE_RESULT (current_cpu, "h-sm", 'x', CPU (h_sm));
+  TRACE_RESULT (current_cpu, "h-sm-0", 'x', CPU (h_sm));
   CPU (h_ie) = CPU (h_bie);
-  TRACE_RESULT (current_cpu, "h-ie", 'x', CPU (h_ie));
+  TRACE_RESULT (current_cpu, "h-ie-0", 'x', CPU (h_ie));
   CPU (h_cond) = CPU (h_bcond);
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, CPU (h_bpc)));
   taken_p = 1;
   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform seth: seth $dr,$hi16.  */
+/* Perform seth: seth $dr,#$hi16.  */
 CIA
 SEM_FN_NAME (m32r,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_38_seth.f
+#define FLD(f) abuf->fields.fmt_39_seth.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = SLLSI (FLD (f_hi16), 16);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1729,58 +1965,67 @@ SEM_FN_NAME (m32r,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = SLLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform sll3: sll3 $dr,$sr,$simm16.  */
+/* Perform sll3: sll3 $dr,$sr,#$simm16.  */
 CIA
 SEM_FN_NAME (m32r,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = SLLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform slli: slli $dr,$uimm5.  */
+/* Perform slli: slli $dr,#$uimm5.  */
 CIA
 SEM_FN_NAME (m32r,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_39_slli.f
+#define FLD(f) abuf->fields.fmt_40_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = SLLSI (* FLD (f_r1), FLD (f_uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1792,58 +2037,67 @@ SEM_FN_NAME (m32r,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = SRASI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform sra3: sra3 $dr,$sr,$simm16.  */
+/* Perform sra3: sra3 $dr,$sr,#$simm16.  */
 CIA
 SEM_FN_NAME (m32r,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = SRASI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform srai: srai $dr,$uimm5.  */
+/* Perform srai: srai $dr,#$uimm5.  */
 CIA
 SEM_FN_NAME (m32r,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_39_slli.f
+#define FLD(f) abuf->fields.fmt_40_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = SRASI (* FLD (f_r1), FLD (f_uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1855,58 +2109,67 @@ SEM_FN_NAME (m32r,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = SRLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform srl3: srl3 $dr,$sr,$simm16.  */
+/* Perform srl3: srl3 $dr,$sr,#$simm16.  */
 CIA
 SEM_FN_NAME (m32r,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = SRLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform srli: srli $dr,$uimm5.  */
+/* Perform srli: srli $dr,#$uimm5.  */
 CIA
 SEM_FN_NAME (m32r,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_39_slli.f
+#define FLD(f) abuf->fields.fmt_40_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = SRLSI (* FLD (f_r1), FLD (f_uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1918,15 +2181,18 @@ SEM_FN_NAME (m32r,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1935,18 +2201,21 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
 CIA
 SEM_FN_NAME (m32r,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_40_st_d.f
+#define FLD(f) abuf->fields.fmt_41_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+  TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1958,15 +2227,18 @@ SEM_FN_NAME (m32r,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMQI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMQI (current_cpu, * FLD (f_r2)));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1975,18 +2247,21 @@ SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1));
 CIA
 SEM_FN_NAME (m32r,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_40_st_d.f
+#define FLD(f) abuf->fields.fmt_41_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+  TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -1998,15 +2273,18 @@ SEM_FN_NAME (m32r,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMHI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMHI (current_cpu, * FLD (f_r2)));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -2015,18 +2293,21 @@ SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1));
 CIA
 SEM_FN_NAME (m32r,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_40_st_d.f
+#define FLD(f) abuf->fields.fmt_41_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+  TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -2038,19 +2319,22 @@ SEM_FN_NAME (m32r,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do {
 * FLD (f_r2) = ADDSI (* FLD (f_r2), 4);
   TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -2062,19 +2346,22 @@ SEM_FN_NAME (m32r,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do {
 * FLD (f_r2) = SUBSI (* FLD (f_r2), 4);
   TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -2086,16 +2373,19 @@ SEM_FN_NAME (m32r,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 * FLD (f_r1) = SUBSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -2107,6 +2397,7 @@ SEM_FN_NAME (m32r,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do {
   BI temp1;SI temp0;
   temp0 = SUBSI (* FLD (f_r1), * FLD (f_r2));
@@ -2116,14 +2407,16 @@ do {
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -2135,6 +2428,7 @@ SEM_FN_NAME (m32r,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_6_addx.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do {
   BI temp1;SI temp0;
   temp0 = SUBCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
@@ -2144,33 +2438,38 @@ do {
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
       m32r_model_mark_set_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
 
-/* Perform trap: trap $uimm4.  */
+/* Perform trap: trap #$uimm4.  */
 CIA
 SEM_FN_NAME (m32r,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_41_trap.f
+#define FLD(f) abuf->fields.fmt_42_trap.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
   int taken_p = 0;
+
 do_trap (current_cpu, FLD (f_uimm4));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      model_profile_cti_insn (current_cpu, abuf, taken_p);
+      m32r_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
@@ -2182,14 +2481,17 @@ SEM_FN_NAME (m32r,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = SEM_NEXT_PC (sem_arg);
+
 do_unlock (current_cpu, * FLD (f_r1), * FLD (f_r2));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32r_model_mark_get_h_gr (current_cpu, abuf);
-      model_profile_insn (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef FLD
 }
diff --git a/sim/m32r/semx.c b/sim/m32r/semx.c
index efe9fe5..eefa8a1 100644
--- a/sim/m32r/semx.c
+++ b/sim/m32r/semx.c
@@ -1,5 +1,7 @@
 /* Simulator instruction semantics for m32rx.
 
+This file is machine generated with CGEN.
+
 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of the GNU Simulators.
@@ -37,12 +39,16 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 CIA
 SEM_FN_NAME (m32rx,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
   CPU (h_gr[f_r1]) = ADDSI (OPRND (dr), OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -51,21 +57,25 @@ SEM_FN_NAME (m32rx,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform add3: add3 $dr,$sr,#$slo16.  */
 CIA
 SEM_FN_NAME (m32rx,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_1_add3.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_1_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_1_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_1_ADD3_CODE
+
   CPU (h_gr[f_r1]) = ADDSI (OPRND (sr), OPRND (slo16));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -74,21 +84,25 @@ SEM_FN_NAME (m32rx,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform and: and $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
   CPU (h_gr[f_r1]) = ANDSI (OPRND (dr), OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -97,21 +111,25 @@ SEM_FN_NAME (m32rx,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform and3: and3 $dr,$sr,#$uimm16.  */
 CIA
 SEM_FN_NAME (m32rx,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_2_and3.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_2_and3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_2_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_2_AND3_CODE
+
   CPU (h_gr[f_r1]) = ANDSI (OPRND (sr), OPRND (uimm16));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -120,21 +138,25 @@ SEM_FN_NAME (m32rx,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform or: or $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
   CPU (h_gr[f_r1]) = ORSI (OPRND (dr), OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -143,21 +165,25 @@ SEM_FN_NAME (m32rx,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform or3: or3 $dr,$sr,#$ulo16.  */
 CIA
 SEM_FN_NAME (m32rx,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_3_or3.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_3_or3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_3_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_3_OR3_CODE
+
   CPU (h_gr[f_r1]) = ORSI (OPRND (sr), OPRND (ulo16));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -166,21 +192,25 @@ SEM_FN_NAME (m32rx,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform xor: xor $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
   CPU (h_gr[f_r1]) = XORSI (OPRND (dr), OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -189,21 +219,25 @@ SEM_FN_NAME (m32rx,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform xor3: xor3 $dr,$sr,#$uimm16.  */
 CIA
 SEM_FN_NAME (m32rx,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_2_and3.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_2_and3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_2_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_2_AND3_CODE
+
   CPU (h_gr[f_r1]) = XORSI (OPRND (sr), OPRND (uimm16));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -212,21 +246,25 @@ SEM_FN_NAME (m32rx,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform addi: addi $dr,#$simm8.  */
 CIA
 SEM_FN_NAME (m32rx,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_4_addi.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_4_addi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_4_ADDI_VARS /* f-op1 f-r1 f-simm8 */
+  EXTRACT_FMT_4_ADDI_CODE
+
   CPU (h_gr[f_r1]) = ADDSI (OPRND (dr), OPRND (simm8));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -235,28 +273,32 @@ SEM_FN_NAME (m32rx,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform addv: addv $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
 do {
   BI temp1;SI temp0;
   temp0 = ADDSI (OPRND (dr), OPRND (sr));
   temp1 = ADDOFSI (OPRND (dr), OPRND (sr), 0);
   CPU (h_gr[f_r1]) = temp0;
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
   CPU (h_cond) = temp1;
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -265,28 +307,32 @@ do {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform addv3: addv3 $dr,$sr,#$simm16.  */
 CIA
 SEM_FN_NAME (m32rx,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_5_addv3.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_5_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_5_ADDV3_CODE
+
 do {
   BI temp1;SI temp0;
   temp0 = ADDSI (OPRND (sr), OPRND (simm16));
   temp1 = ADDOFSI (OPRND (sr), OPRND (simm16), 0);
   CPU (h_gr[f_r1]) = temp0;
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
   CPU (h_cond) = temp1;
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -295,28 +341,32 @@ do {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform addx: addx $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_6_addx.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_6_addx.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_6_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_6_ADDX_CODE
+
 do {
   BI temp1;SI temp0;
   temp0 = ADDCSI (OPRND (dr), OPRND (sr), OPRND (condbit));
   temp1 = ADDCFSI (OPRND (dr), OPRND (sr), OPRND (condbit));
   CPU (h_gr[f_r1]) = temp0;
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
   CPU (h_cond) = temp1;
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -325,69 +375,81 @@ do {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bc8: bc $disp8.  */
 CIA
 SEM_FN_NAME (m32rx,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_7_bc8.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_7_bc8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_7_BC8_VARS /* f-op1 f-r1 f-disp8 */
+  EXTRACT_FMT_7_BC8_CODE
+
 if (OPRND (condbit)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bc24: bc $disp24.  */
 CIA
 SEM_FN_NAME (m32rx,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_8_bc24.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_8_bc24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_8_BC24_VARS /* f-op1 f-r1 f-disp24 */
+  EXTRACT_FMT_8_BC24_CODE
+
 if (OPRND (condbit)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform beq: beq $src1,$src2,$disp16.  */
 CIA
 SEM_FN_NAME (m32rx,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_9_beq.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_9_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_9_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+  EXTRACT_FMT_9_BEQ_CODE
+
 if (EQSI (OPRND (src1), OPRND (src2))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -395,23 +457,27 @@ if (EQSI (OPRND (src1), OPRND (src2))) {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform beqz: beqz $src2,$disp16.  */
 CIA
 SEM_FN_NAME (m32rx,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_10_beqz.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_10_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+  EXTRACT_FMT_10_BEQZ_CODE
+
 if (EQSI (OPRND (src2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -419,23 +485,27 @@ if (EQSI (OPRND (src2), 0)) {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bgez: bgez $src2,$disp16.  */
 CIA
 SEM_FN_NAME (m32rx,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_10_beqz.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_10_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+  EXTRACT_FMT_10_BEQZ_CODE
+
 if (GESI (OPRND (src2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -443,23 +513,27 @@ if (GESI (OPRND (src2), 0)) {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bgtz: bgtz $src2,$disp16.  */
 CIA
 SEM_FN_NAME (m32rx,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_10_beqz.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_10_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+  EXTRACT_FMT_10_BEQZ_CODE
+
 if (GTSI (OPRND (src2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -467,23 +541,27 @@ if (GTSI (OPRND (src2), 0)) {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform blez: blez $src2,$disp16.  */
 CIA
 SEM_FN_NAME (m32rx,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_10_beqz.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_10_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+  EXTRACT_FMT_10_BEQZ_CODE
+
 if (LESI (OPRND (src2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -491,23 +569,27 @@ if (LESI (OPRND (src2), 0)) {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bltz: bltz $src2,$disp16.  */
 CIA
 SEM_FN_NAME (m32rx,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_10_beqz.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_10_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+  EXTRACT_FMT_10_BEQZ_CODE
+
 if (LTSI (OPRND (src2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -515,23 +597,27 @@ if (LTSI (OPRND (src2), 0)) {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bnez: bnez $src2,$disp16.  */
 CIA
 SEM_FN_NAME (m32rx,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_10_beqz.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_10_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+  EXTRACT_FMT_10_BEQZ_CODE
+
 if (NESI (OPRND (src2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -539,77 +625,91 @@ if (NESI (OPRND (src2), 0)) {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bl8: bl $disp8.  */
 CIA
 SEM_FN_NAME (m32rx,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_11_bl8.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_11_bl8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_11_BL8_VARS /* f-op1 f-r1 f-disp8 */
+  EXTRACT_FMT_11_BL8_CODE
+
 do {
   CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
-  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bl24: bl $disp24.  */
 CIA
 SEM_FN_NAME (m32rx,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_12_bl24.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_12_bl24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_12_BL24_VARS /* f-op1 f-r1 f-disp24 */
+  EXTRACT_FMT_12_BL24_CODE
+
 do {
   CPU (h_gr[14]) = ADDSI (OPRND (pc), 4);
-  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bcl8: bcl $disp8.  */
 CIA
 SEM_FN_NAME (m32rx,bcl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_13_bcl8.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_13_bcl8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_13_BCL8_VARS /* f-op1 f-r1 f-disp8 */
+  EXTRACT_FMT_13_BCL8_CODE
+
 if (OPRND (condbit)) {
 do {
   CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
-  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
 } while (0);
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -617,27 +717,31 @@ do {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bcl24: bcl $disp24.  */
 CIA
 SEM_FN_NAME (m32rx,bcl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_14_bcl24.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_14_bcl24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_14_BCL24_VARS /* f-op1 f-r1 f-disp24 */
+  EXTRACT_FMT_14_BCL24_CODE
+
 if (OPRND (condbit)) {
 do {
   CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
-  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
 } while (0);
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -645,69 +749,81 @@ do {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bnc8: bnc $disp8.  */
 CIA
 SEM_FN_NAME (m32rx,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_7_bc8.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_7_bc8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_7_BC8_VARS /* f-op1 f-r1 f-disp8 */
+  EXTRACT_FMT_7_BC8_CODE
+
 if (NOTBI (OPRND (condbit))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bnc24: bnc $disp24.  */
 CIA
 SEM_FN_NAME (m32rx,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_8_bc24.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_8_bc24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_8_BC24_VARS /* f-op1 f-r1 f-disp24 */
+  EXTRACT_FMT_8_BC24_CODE
+
 if (NOTBI (OPRND (condbit))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bne: bne $src1,$src2,$disp16.  */
 CIA
 SEM_FN_NAME (m32rx,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_9_beq.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_9_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_9_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+  EXTRACT_FMT_9_BEQ_CODE
+
 if (NESI (OPRND (src1), OPRND (src2))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -715,69 +831,81 @@ if (NESI (OPRND (src1), OPRND (src2))) {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bra8: bra $disp8.  */
 CIA
 SEM_FN_NAME (m32rx,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_15_bra8.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_15_bra8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_15_BRA8_VARS /* f-op1 f-r1 f-disp8 */
+  EXTRACT_FMT_15_BRA8_CODE
+
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bra24: bra $disp24.  */
 CIA
 SEM_FN_NAME (m32rx,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_16_bra24.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_16_bra24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_16_BRA24_VARS /* f-op1 f-r1 f-disp24 */
+  EXTRACT_FMT_16_BRA24_CODE
+
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bncl8: bncl $disp8.  */
 CIA
 SEM_FN_NAME (m32rx,bncl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_13_bcl8.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_13_bcl8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_13_BCL8_VARS /* f-op1 f-r1 f-disp8 */
+  EXTRACT_FMT_13_BCL8_CODE
+
 if (NOTBI (OPRND (condbit))) {
 do {
   CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
-  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
 } while (0);
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -785,27 +913,31 @@ do {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform bncl24: bncl $disp24.  */
 CIA
 SEM_FN_NAME (m32rx,bncl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_14_bcl24.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_14_bcl24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
   int taken_p = 0;
+  EXTRACT_FMT_14_BCL24_VARS /* f-op1 f-r1 f-disp24 */
+  EXTRACT_FMT_14_BCL24_CODE
+
 if (NOTBI (OPRND (condbit))) {
 do {
   CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
-  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
 } while (0);
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -813,21 +945,25 @@ do {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform cmp: cmp $src1,$src2.  */
 CIA
 SEM_FN_NAME (m32rx,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_17_cmp.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_17_CMP_CODE
+
   CPU (h_cond) = LTSI (OPRND (src1), OPRND (src2));
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -835,21 +971,25 @@ SEM_FN_NAME (m32rx,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform cmpi: cmpi $src2,#$simm16.  */
 CIA
 SEM_FN_NAME (m32rx,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_18_cmpi.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_18_cmpi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_18_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_18_CMPI_CODE
+
   CPU (h_cond) = LTSI (OPRND (src2), OPRND (simm16));
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -857,21 +997,25 @@ SEM_FN_NAME (m32rx,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform cmpu: cmpu $src1,$src2.  */
 CIA
 SEM_FN_NAME (m32rx,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_17_cmp.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_17_CMP_CODE
+
   CPU (h_cond) = LTUSI (OPRND (src1), OPRND (src2));
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -879,21 +1023,25 @@ SEM_FN_NAME (m32rx,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform cmpui: cmpui $src2,#$uimm16.  */
 CIA
 SEM_FN_NAME (m32rx,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_19_cmpui.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_19_cmpui.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_19_CMPUI_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_19_CMPUI_CODE
+
   CPU (h_cond) = LTUSI (OPRND (src2), OPRND (uimm16));
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -901,21 +1049,25 @@ SEM_FN_NAME (m32rx,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform cmpeq: cmpeq $src1,$src2.  */
 CIA
 SEM_FN_NAME (m32rx,cmpeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_17_cmp.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_17_CMP_CODE
+
   CPU (h_cond) = EQSI (OPRND (src1), OPRND (src2));
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -923,21 +1075,25 @@ SEM_FN_NAME (m32rx,cmpeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform cmpz: cmpz $src2.  */
 CIA
 SEM_FN_NAME (m32rx,cmpz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_20_cmpz.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_20_cmpz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_20_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_20_CMPZ_CODE
+
   CPU (h_cond) = EQSI (OPRND (src2), 0);
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -945,23 +1101,27 @@ SEM_FN_NAME (m32rx,cmpz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform div: div $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_21_div.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_21_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_21_DIV_CODE
+
 if (NESI (OPRND (sr), 0)) {
   CPU (h_gr[f_r1]) = DIVSI (OPRND (dr), OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -970,23 +1130,27 @@ if (NESI (OPRND (sr), 0)) {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform divu: divu $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_21_div.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_21_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_21_DIV_CODE
+
 if (NESI (OPRND (sr), 0)) {
   CPU (h_gr[f_r1]) = UDIVSI (OPRND (dr), OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -995,23 +1159,27 @@ if (NESI (OPRND (sr), 0)) {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform rem: rem $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_21_div.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_21_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_21_DIV_CODE
+
 if (NESI (OPRND (sr), 0)) {
   CPU (h_gr[f_r1]) = MODSI (OPRND (dr), OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1020,23 +1188,27 @@ if (NESI (OPRND (sr), 0)) {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform remu: remu $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_21_div.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_21_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_21_DIV_CODE
+
 if (NESI (OPRND (sr), 0)) {
   CPU (h_gr[f_r1]) = UMODSI (OPRND (dr), OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1045,23 +1217,27 @@ if (NESI (OPRND (sr), 0)) {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform jc: jc $sr.  */
 CIA
 SEM_FN_NAME (m32rx,jc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_22_jc.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_22_jc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_22_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_22_JC_CODE
+
 if (OPRND (condbit)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (OPRND (sr), -4)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1069,23 +1245,27 @@ if (OPRND (condbit)) {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform jnc: jnc $sr.  */
 CIA
 SEM_FN_NAME (m32rx,jnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_22_jc.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_22_jc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_22_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_22_JC_CODE
+
 if (NOTBI (OPRND (condbit))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (OPRND (sr), -4)));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1093,50 +1273,59 @@ if (NOTBI (OPRND (condbit))) {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform jl: jl $sr.  */
 CIA
 SEM_FN_NAME (m32rx,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_23_jl.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_23_jl.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_23_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_23_JL_CODE
+
 do {
   USI temp1;SI temp0;
   temp0 = ADDSI (ANDSI (OPRND (pc), -4), 4);
   temp1 = OPRND (sr);
   CPU (h_gr[14]) = temp0;
-  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform jmp: jmp $sr.  */
 CIA
 SEM_FN_NAME (m32rx,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_24_jmp.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_24_jmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_24_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_24_JMP_CODE
+
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, OPRND (sr)));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1144,21 +1333,25 @@ SEM_FN_NAME (m32rx,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ld: ld $dr,@$sr.  */
 CIA
 SEM_FN_NAME (m32rx,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_25_ld.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_25_ld.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = OPRND (h_memory);
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_25_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_25_LD_CODE
+
+  CPU (h_gr[f_r1]) = OPRND (h_memory_sr);
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1167,21 +1360,25 @@ SEM_FN_NAME (m32rx,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ld-d: ld $dr,@($slo16,$sr).  */
 CIA
 SEM_FN_NAME (m32rx,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_26_ld_d.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_26_ld_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = OPRND (h_memory);
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_26_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_26_LD_D_CODE
+
+  CPU (h_gr[f_r1]) = OPRND (h_memory_add_WI_sr_slo16);
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1190,21 +1387,25 @@ SEM_FN_NAME (m32rx,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ldb: ldb $dr,@$sr.  */
 CIA
 SEM_FN_NAME (m32rx,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_27_ldb.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_27_ldb.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = EXTQISI (OPRND (h_memory));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_27_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_27_LDB_CODE
+
+  CPU (h_gr[f_r1]) = EXTQISI (OPRND (h_memory_sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1213,21 +1414,25 @@ SEM_FN_NAME (m32rx,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ldb-d: ldb $dr,@($slo16,$sr).  */
 CIA
 SEM_FN_NAME (m32rx,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_28_ldb_d.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_28_ldb_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = EXTQISI (OPRND (h_memory));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_28_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_28_LDB_D_CODE
+
+  CPU (h_gr[f_r1]) = EXTQISI (OPRND (h_memory_add_WI_sr_slo16));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1236,21 +1441,25 @@ SEM_FN_NAME (m32rx,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ldh: ldh $dr,@$sr.  */
 CIA
 SEM_FN_NAME (m32rx,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_29_ldh.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_29_ldh.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = EXTHISI (OPRND (h_memory));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_29_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_29_LDH_CODE
+
+  CPU (h_gr[f_r1]) = EXTHISI (OPRND (h_memory_sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1259,21 +1468,25 @@ SEM_FN_NAME (m32rx,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ldh-d: ldh $dr,@($slo16,$sr).  */
 CIA
 SEM_FN_NAME (m32rx,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_30_ldh_d.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_30_ldh_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = EXTHISI (OPRND (h_memory));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_30_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_30_LDH_D_CODE
+
+  CPU (h_gr[f_r1]) = EXTHISI (OPRND (h_memory_add_WI_sr_slo16));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1282,21 +1495,25 @@ SEM_FN_NAME (m32rx,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ldub: ldub $dr,@$sr.  */
 CIA
 SEM_FN_NAME (m32rx,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_27_ldb.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_27_ldb.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = ZEXTQISI (OPRND (h_memory));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_27_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_27_LDB_CODE
+
+  CPU (h_gr[f_r1]) = ZEXTQISI (OPRND (h_memory_sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1305,21 +1522,25 @@ SEM_FN_NAME (m32rx,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ldub-d: ldub $dr,@($slo16,$sr).  */
 CIA
 SEM_FN_NAME (m32rx,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_28_ldb_d.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_28_ldb_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = ZEXTQISI (OPRND (h_memory));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_28_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_28_LDB_D_CODE
+
+  CPU (h_gr[f_r1]) = ZEXTQISI (OPRND (h_memory_add_WI_sr_slo16));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1328,21 +1549,25 @@ SEM_FN_NAME (m32rx,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform lduh: lduh $dr,@$sr.  */
 CIA
 SEM_FN_NAME (m32rx,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_29_ldh.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_29_ldh.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = ZEXTHISI (OPRND (h_memory));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_29_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_29_LDH_CODE
+
+  CPU (h_gr[f_r1]) = ZEXTHISI (OPRND (h_memory_sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1351,21 +1576,25 @@ SEM_FN_NAME (m32rx,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform lduh-d: lduh $dr,@($slo16,$sr).  */
 CIA
 SEM_FN_NAME (m32rx,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_30_ldh_d.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_30_ldh_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = ZEXTHISI (OPRND (h_memory));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_30_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_30_LDH_D_CODE
+
+  CPU (h_gr[f_r1]) = ZEXTHISI (OPRND (h_memory_add_WI_sr_slo16));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1374,28 +1603,32 @@ SEM_FN_NAME (m32rx,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ld-plus: ld $dr,@$sr+.  */
 CIA
 SEM_FN_NAME (m32rx,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_25_ld.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_25_ld.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_25_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_25_LD_CODE
+
 do {
   SI temp1;SI temp0;
-  temp0 = OPRND (h_memory);
+  temp0 = OPRND (h_memory_sr);
   temp1 = ADDSI (OPRND (sr), 4);
   CPU (h_gr[f_r1]) = temp0;
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
   CPU (h_gr[f_r2]) = temp1;
-  TRACE_RESULT (current_cpu, "sr", 'x', OPRND (sr));
+  TRACE_RESULT (current_cpu, "sr", 'x', CPU (h_gr[f_r2]));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1404,21 +1637,25 @@ do {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ld24: ld24 $dr,#$uimm24.  */
 CIA
 SEM_FN_NAME (m32rx,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_31_ld24.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_31_ld24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_31_LD24_VARS /* f-op1 f-r1 f-uimm24 */
+  EXTRACT_FMT_31_LD24_CODE
+
   CPU (h_gr[f_r1]) = OPRND (uimm24);
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1426,21 +1663,25 @@ SEM_FN_NAME (m32rx,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ldi8: ldi $dr,#$simm8.  */
 CIA
 SEM_FN_NAME (m32rx,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_32_ldi8.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_32_ldi8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_32_LDI8_VARS /* f-op1 f-r1 f-simm8 */
+  EXTRACT_FMT_32_LDI8_CODE
+
   CPU (h_gr[f_r1]) = OPRND (simm8);
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1448,21 +1689,25 @@ SEM_FN_NAME (m32rx,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform ldi16: ldi $dr,$slo16.  */
 CIA
 SEM_FN_NAME (m32rx,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_33_ldi16.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_33_ldi16.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_33_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_33_LDI16_CODE
+
   CPU (h_gr[f_r1]) = OPRND (slo16);
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1470,20 +1715,24 @@ SEM_FN_NAME (m32rx,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform lock: lock $dr,@$sr.  */
 CIA
 SEM_FN_NAME (m32rx,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
 do_lock (current_cpu, OPRND (dr), OPRND (sr));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1492,21 +1741,25 @@ do_lock (current_cpu, OPRND (dr), OPRND (sr));
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
-/* Perform machi: machi $src1,$src2.  */
+/* Perform machi-a: machi $src1,$src2,$acc.  */
 CIA
-SEM_FN_NAME (m32rx,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (m32rx,machi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_34_machi.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi_a.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8);
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_34_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
+  EXTRACT_FMT_34_MACHI_A_CODE
+
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8));
+  TRACE_RESULT (current_cpu, "acc", 'D', m32rx_h_accums_get (current_cpu, f_acc));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1514,21 +1767,25 @@ SEM_FN_NAME (m32rx,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
-/* Perform machi-a: machi $src1,$src2,$acc.  */
+/* Perform maclo-a: maclo $src1,$src2,$acc.  */
 CIA
-SEM_FN_NAME (m32rx,machi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (m32rx,maclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_35_machi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi_a.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8));
-  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_34_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
+  EXTRACT_FMT_34_MACHI_A_CODE
+
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8));
+  TRACE_RESULT (current_cpu, "acc", 'D', m32rx_h_accums_get (current_cpu, f_acc));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1536,43 +1793,52 @@ m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
-/* Perform maclo: maclo $src1,$src2.  */
+/* Perform mul: mul $dr,$sr.  */
 CIA
-SEM_FN_NAME (m32rx,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (m32rx,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_34_machi.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8);
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
+  CPU (h_gr[f_r1]) = MULSI (OPRND (dr), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
-/* Perform maclo-a: maclo $src1,$src2,$acc.  */
+/* Perform mulhi-a: mulhi $src1,$src2,$acc.  */
 CIA
-SEM_FN_NAME (m32rx,maclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (m32rx,mulhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_35_machi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_mulhi_a.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8));
-  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_35_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
+  EXTRACT_FMT_35_MULHI_A_CODE
+
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 16), 16));
+  TRACE_RESULT (current_cpu, "acc", 'D', m32rx_h_accums_get (current_cpu, f_acc));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1580,21 +1846,25 @@ m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
-/* Perform macwhi: macwhi $src1,$src2.  */
+/* Perform mullo-a: mullo $src1,$src2,$acc.  */
 CIA
-SEM_FN_NAME (m32rx,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (m32rx,mullo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_34_machi.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_mulhi_a.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8);
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_35_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
+  EXTRACT_FMT_35_MULHI_A_CODE
+
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 16), 16));
+  TRACE_RESULT (current_cpu, "acc", 'D', m32rx_h_accums_get (current_cpu, f_acc));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1602,375 +1872,104 @@ SEM_FN_NAME (m32rx,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
-/* Perform macwhi-a: macwhi $src1,$src2,$acc.  */
+/* Perform mv: mv $dr,$sr.  */
 CIA
-SEM_FN_NAME (m32rx,macwhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (m32rx,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_35_machi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mv.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8));
-  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_36_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_36_MV_CODE
+
+  CPU (h_gr[f_r1]) = OPRND (sr);
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
-/* Perform macwlo: macwlo $src1,$src2.  */
+/* Perform mvfachi-a: mvfachi $dr,$accs.  */
 CIA
-SEM_FN_NAME (m32rx,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (m32rx,mvfachi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_34_machi.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mvfachi_a.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8);
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_37_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+  EXTRACT_FMT_37_MVFACHI_A_CODE
+
+  CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accs), 32));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
-/* Perform macwlo-a: macwlo $src1,$src2,$acc.  */
+/* Perform mvfaclo-a: mvfaclo $dr,$accs.  */
 CIA
-SEM_FN_NAME (m32rx,macwlo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (m32rx,mvfaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_35_machi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mvfachi_a.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8));
-  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_37_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+  EXTRACT_FMT_37_MVFACHI_A_CODE
+
+  CPU (h_gr[f_r1]) = TRUNCDISI (OPRND (accs));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
-/* Perform mul: mul $dr,$sr.  */
+/* Perform mvfacmi-a: mvfacmi $dr,$accs.  */
 CIA
-SEM_FN_NAME (m32rx,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (m32rx,mvfacmi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mvfachi_a.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = MULSI (OPRND (dr), OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_mark_set_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
-
-/* Perform mulhi: mulhi $src1,$src2.  */
-CIA
-SEM_FN_NAME (m32rx,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_17_cmp.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 16), 16);
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
-
-/* Perform mulhi-a: mulhi $src1,$src2,$acc.  */
-CIA
-SEM_FN_NAME (m32rx,mulhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_36_mulhi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 16), 16));
-  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
-
-/* Perform mullo: mullo $src1,$src2.  */
-CIA
-SEM_FN_NAME (m32rx,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_17_cmp.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 16), 16);
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
-
-/* Perform mullo-a: mullo $src1,$src2,$acc.  */
-CIA
-SEM_FN_NAME (m32rx,mullo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_36_mulhi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 16), 16));
-  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_37_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+  EXTRACT_FMT_37_MVFACHI_A_CODE
 
-/* Perform mulwhi: mulwhi $src1,$src2.  */
-CIA
-SEM_FN_NAME (m32rx,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_17_cmp.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 8), 8);
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
-
-/* Perform mulwhi-a: mulwhi $src1,$src2,$acc.  */
-CIA
-SEM_FN_NAME (m32rx,mulwhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_36_mulhi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 8), 8));
-  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
-
-/* Perform mulwlo: mulwlo $src1,$src2.  */
-CIA
-SEM_FN_NAME (m32rx,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_17_cmp.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 8), 8);
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
-
-/* Perform mulwlo-a: mulwlo $src1,$src2,$acc.  */
-CIA
-SEM_FN_NAME (m32rx,mulwlo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_36_mulhi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 8), 8));
-  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
-
-/* Perform mv: mv $dr,$sr.  */
-CIA
-SEM_FN_NAME (m32rx,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_37_mv.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = OPRND (sr);
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_mark_set_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
-
-/* Perform mvfachi: mvfachi $dr.  */
-CIA
-SEM_FN_NAME (m32rx,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_38_mvfachi.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accum), 32));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_set_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
-
-/* Perform mvfachi-a: mvfachi $dr,$accs.  */
-CIA
-SEM_FN_NAME (m32rx,mvfachi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_39_mvfachi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accs), 32));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_set_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
-
-/* Perform mvfaclo: mvfaclo $dr.  */
-CIA
-SEM_FN_NAME (m32rx,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_38_mvfachi.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = TRUNCDISI (OPRND (accum));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_set_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
+  CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accs), 16));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 
-/* Perform mvfaclo-a: mvfaclo $dr,$accs.  */
-CIA
-SEM_FN_NAME (m32rx,mvfaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_39_mvfachi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = TRUNCDISI (OPRND (accs));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -1978,65 +1977,25 @@ SEM_FN_NAME (m32rx,mvfaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
 
-/* Perform mvfacmi: mvfacmi $dr.  */
-CIA
-SEM_FN_NAME (m32rx,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_38_mvfachi.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accum), 16));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_set_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
   return new_pc;
 #undef OPRND
-#undef FLD
-}
-
-/* Perform mvfacmi-a: mvfacmi $dr,$accs.  */
-CIA
-SEM_FN_NAME (m32rx,mvfacmi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_39_mvfachi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accs), 16));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_set_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
 }
 
 /* Perform mvfc: mvfc $dr,$scr.  */
 CIA
 SEM_FN_NAME (m32rx,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_40_mvfc.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_40_mvfc.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_38_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_38_MVFC_CODE
+
   CPU (h_gr[f_r1]) = OPRND (scr);
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2044,65 +2003,25 @@ SEM_FN_NAME (m32rx,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
 
-/* Perform mvtachi: mvtachi $src1.  */
-CIA
-SEM_FN_NAME (m32rx,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_41_mvtachi.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_mvtachi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_accum) = ORDI (ANDDI (OPRND (accum), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (OPRND (src1)), 32));
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform mvtachi-a: mvtachi $src1,$accs.  */
 CIA
 SEM_FN_NAME (m32rx,mvtachi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_42_mvtachi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_mvtachi_a.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvtachi_a.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_39_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+  EXTRACT_FMT_39_MVTACHI_A_CODE
+
 m32rx_h_accums_set (current_cpu, f_accs, ORDI (ANDDI (OPRND (accs), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (OPRND (src1)), 32)));
-  TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs));
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_mark_get_h_gr (current_cpu, abuf);
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
+  TRACE_RESULT (current_cpu, "accs", 'D', m32rx_h_accums_get (current_cpu, f_accs));
 
-/* Perform mvtaclo: mvtaclo $src1.  */
-CIA
-SEM_FN_NAME (m32rx,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_41_mvtachi.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_mvtachi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-  CPU (h_accum) = ORDI (ANDDI (OPRND (accum), MAKEDI (0xffffffff, 0)), EXTSIDI (OPRND (src1)));
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2110,21 +2029,25 @@ SEM_FN_NAME (m32rx,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform mvtaclo-a: mvtaclo $src1,$accs.  */
 CIA
 SEM_FN_NAME (m32rx,mvtaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_42_mvtachi_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_mvtachi_a.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvtachi_a.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_39_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+  EXTRACT_FMT_39_MVTACHI_A_CODE
+
 m32rx_h_accums_set (current_cpu, f_accs, ORDI (ANDDI (OPRND (accs), MAKEDI (0xffffffff, 0)), EXTSIDI (OPRND (src1))));
-  TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs));
+  TRACE_RESULT (current_cpu, "accs", 'D', m32rx_h_accums_get (current_cpu, f_accs));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2132,21 +2055,25 @@ m32rx_h_accums_set (current_cpu, f_accs, ORDI (ANDDI (OPRND (accs), MAKEDI (0xff
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform mvtc: mvtc $sr,$dcr.  */
 CIA
 SEM_FN_NAME (m32rx,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_43_mvtc.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_43_mvtc.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_40_mvtc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_40_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_40_MVTC_CODE
+
 m32rx_h_cr_set (current_cpu, f_r1, OPRND (sr));
-  TRACE_RESULT (current_cpu, "dcr", 'x', OPRND (dcr));
+  TRACE_RESULT (current_cpu, "dcr", 'x', m32rx_h_cr_get (current_cpu, f_r1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2154,21 +2081,25 @@ m32rx_h_cr_set (current_cpu, f_r1, OPRND (sr));
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform neg: neg $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_37_mv.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mv.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_36_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_36_MV_CODE
+
   CPU (h_gr[f_r1]) = NEGSI (OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2177,41 +2108,49 @@ SEM_FN_NAME (m32rx,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform nop: nop.  */
 CIA
 SEM_FN_NAME (m32rx,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_44_nop.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_nop.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_nop.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_41_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_41_NOP_CODE
+
 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform not: not $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_37_mv.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mv.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_36_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_36_MV_CODE
+
   CPU (h_gr[f_r1]) = INVSI (OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2220,54 +2159,22 @@ SEM_FN_NAME (m32rx,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
 
-/* Perform rac: rac.  */
-CIA
-SEM_FN_NAME (m32rx,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_45_rac.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_rac.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-do {
-  DI tmp_tmp1;
-  tmp_tmp1 = ANDDI (OPRND (accum), MAKEDI (16777215, 0xffffffff));
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0xffff8000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
-  tmp_tmp1 = MAKEDI (16383, 0xffff8000);
-} else {
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
-  tmp_tmp1 = MAKEDI (16760832, 0);
-} else {
-  tmp_tmp1 = ANDDI (ADDDI (OPRND (accum), MAKEDI (0, 16384)), MAKEDI (16777215, 0xffff8000));
-}
-}
-  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
-  CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
-} while (0);
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform rac-a: rac $accs.  */
 CIA
 SEM_FN_NAME (m32rx,rac_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_46_rac_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_rac_a.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_rac_a.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_42_RAC_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+  EXTRACT_FMT_42_RAC_A_CODE
+
 do {
   DI tmp_tmp1;
   tmp_tmp1 = ANDDI (OPRND (accs), MAKEDI (16777215, 0xffffffff));
@@ -2282,62 +2189,31 @@ if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760
 }
   tmp_tmp1 = SLLDI (tmp_tmp1, 1);
 m32rx_h_accums_set (current_cpu, f_accs, SRADI (SLLDI (tmp_tmp1, 7), 7));
-  TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs));
+  TRACE_RESULT (current_cpu, "accs", 'D', m32rx_h_accums_get (current_cpu, f_accs));
 } while (0);
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rx_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-  return new_pc;
-#undef OPRND
-#undef FLD
-}
 
-/* Perform rach: rach.  */
-CIA
-SEM_FN_NAME (m32rx,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_45_rac.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_rac.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-do {
-  DI tmp_tmp1;
-  tmp_tmp1 = ANDDI (OPRND (accum), MAKEDI (16777215, 0xffffffff));
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
-  tmp_tmp1 = MAKEDI (16383, 0x80000000);
-} else {
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
-  tmp_tmp1 = MAKEDI (16760832, 0);
-} else {
-  tmp_tmp1 = ANDDI (ADDDI (OPRND (accum), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
-}
-}
-  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
-  CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
-} while (0);
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform rach-a: rach $accs.  */
 CIA
 SEM_FN_NAME (m32rx,rach_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_46_rac_a.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_rac_a.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_rac_a.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_42_RAC_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+  EXTRACT_FMT_42_RAC_A_CODE
+
 do {
   DI tmp_tmp1;
   tmp_tmp1 = ANDDI (OPRND (accs), MAKEDI (16777215, 0xffffffff));
@@ -2352,59 +2228,68 @@ if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760
 }
   tmp_tmp1 = SLLDI (tmp_tmp1, 1);
 m32rx_h_accums_set (current_cpu, f_accs, SRADI (SLLDI (tmp_tmp1, 7), 7));
-  TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs));
+  TRACE_RESULT (current_cpu, "accs", 'D', m32rx_h_accums_get (current_cpu, f_accs));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform rte: rte.  */
 CIA
 SEM_FN_NAME (m32rx,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_44_nop.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_nop.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_43_rte.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_43_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_43_RTE_CODE
+
 do {
-  CPU (h_sm) = OPRND (h_bsm);
-  TRACE_RESULT (current_cpu, "h-sm", 'x', OPRND (h_sm));
-  CPU (h_ie) = OPRND (h_bie);
-  TRACE_RESULT (current_cpu, "h-ie", 'x', OPRND (h_ie));
-  CPU (h_cond) = OPRND (h_bcond);
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
-  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, OPRND (h_bpc)));
-  TRACE_RESULT (current_cpu, "pc", 'x', OPRND (pc));
+  CPU (h_sm) = OPRND (h_bsm_0);
+  TRACE_RESULT (current_cpu, "h-sm-0", 'x', CPU (h_sm));
+  CPU (h_ie) = OPRND (h_bie_0);
+  TRACE_RESULT (current_cpu, "h-ie-0", 'x', CPU (h_ie));
+  CPU (h_cond) = OPRND (h_bcond_0);
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, OPRND (h_bpc_0)));
+  TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
-/* Perform seth: seth $dr,$hi16.  */
+/* Perform seth: seth $dr,#$hi16.  */
 CIA
 SEM_FN_NAME (m32rx,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_47_seth.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_47_seth.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_seth.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_44_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
+  EXTRACT_FMT_44_SETH_CODE
+
   CPU (h_gr[f_r1]) = SLLSI (OPRND (hi16), 16);
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2412,21 +2297,25 @@ SEM_FN_NAME (m32rx,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform sll: sll $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
   CPU (h_gr[f_r1]) = SLLSI (OPRND (dr), ANDSI (OPRND (sr), 31));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2435,21 +2324,25 @@ SEM_FN_NAME (m32rx,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform sll3: sll3 $dr,$sr,#$simm16.  */
 CIA
 SEM_FN_NAME (m32rx,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_5_addv3.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_5_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_5_ADDV3_CODE
+
   CPU (h_gr[f_r1]) = SLLSI (OPRND (sr), ANDSI (OPRND (simm16), 31));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2458,21 +2351,25 @@ SEM_FN_NAME (m32rx,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform slli: slli $dr,#$uimm5.  */
 CIA
 SEM_FN_NAME (m32rx,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_48_slli.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_45_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+  EXTRACT_FMT_45_SLLI_CODE
+
   CPU (h_gr[f_r1]) = SLLSI (OPRND (dr), OPRND (uimm5));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2481,21 +2378,25 @@ SEM_FN_NAME (m32rx,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform sra: sra $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
   CPU (h_gr[f_r1]) = SRASI (OPRND (dr), ANDSI (OPRND (sr), 31));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2504,21 +2405,25 @@ SEM_FN_NAME (m32rx,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform sra3: sra3 $dr,$sr,#$simm16.  */
 CIA
 SEM_FN_NAME (m32rx,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_5_addv3.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_5_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_5_ADDV3_CODE
+
   CPU (h_gr[f_r1]) = SRASI (OPRND (sr), ANDSI (OPRND (simm16), 31));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2527,21 +2432,25 @@ SEM_FN_NAME (m32rx,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform srai: srai $dr,#$uimm5.  */
 CIA
 SEM_FN_NAME (m32rx,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_48_slli.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_45_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+  EXTRACT_FMT_45_SLLI_CODE
+
   CPU (h_gr[f_r1]) = SRASI (OPRND (dr), OPRND (uimm5));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2550,21 +2459,25 @@ SEM_FN_NAME (m32rx,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform srl: srl $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
   CPU (h_gr[f_r1]) = SRLSI (OPRND (dr), ANDSI (OPRND (sr), 31));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2573,21 +2486,25 @@ SEM_FN_NAME (m32rx,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform srl3: srl3 $dr,$sr,#$simm16.  */
 CIA
 SEM_FN_NAME (m32rx,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_5_addv3.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_5_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_5_ADDV3_CODE
+
   CPU (h_gr[f_r1]) = SRLSI (OPRND (sr), ANDSI (OPRND (simm16), 31));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2596,21 +2513,25 @@ SEM_FN_NAME (m32rx,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform srli: srli $dr,#$uimm5.  */
 CIA
 SEM_FN_NAME (m32rx,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_48_slli.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_45_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+  EXTRACT_FMT_45_SLLI_CODE
+
   CPU (h_gr[f_r1]) = SRLSI (OPRND (dr), OPRND (uimm5));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2619,21 +2540,25 @@ SEM_FN_NAME (m32rx,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform st: st $src1,@$src2.  */
 CIA
 SEM_FN_NAME (m32rx,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_17_cmp.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_17_CMP_CODE
+
 SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, OPRND (src2)));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2641,21 +2566,25 @@ SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform st-d: st $src1,@($slo16,$src2).  */
 CIA
 SEM_FN_NAME (m32rx,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_49_st_d.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_46_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_46_ST_D_CODE
+
 SETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2663,21 +2592,25 @@ SETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform stb: stb $src1,@$src2.  */
 CIA
 SEM_FN_NAME (m32rx,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_17_cmp.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_17_CMP_CODE
+
 SETMEMQI (current_cpu, OPRND (src2), OPRND (src1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMQI (current_cpu, OPRND (src2)));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2685,21 +2618,25 @@ SETMEMQI (current_cpu, OPRND (src2), OPRND (src1));
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform stb-d: stb $src1,@($slo16,$src2).  */
 CIA
 SEM_FN_NAME (m32rx,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_49_st_d.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_46_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_46_ST_D_CODE
+
 SETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2707,21 +2644,25 @@ SETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform sth: sth $src1,@$src2.  */
 CIA
 SEM_FN_NAME (m32rx,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_17_cmp.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_17_CMP_CODE
+
 SETMEMHI (current_cpu, OPRND (src2), OPRND (src1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMHI (current_cpu, OPRND (src2)));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2729,21 +2670,25 @@ SETMEMHI (current_cpu, OPRND (src2), OPRND (src1));
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform sth-d: sth $src1,@($slo16,$src2).  */
 CIA
 SEM_FN_NAME (m32rx,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_49_st_d.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_46_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_46_ST_D_CODE
+
 SETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2751,25 +2696,29 @@ SETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform st-plus: st $src1,@+$src2.  */
 CIA
 SEM_FN_NAME (m32rx,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_17_cmp.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_17_CMP_CODE
+
 do {
   CPU (h_gr[f_r2]) = ADDSI (OPRND (src2), 4);
-  TRACE_RESULT (current_cpu, "src2", 'x', OPRND (src2));
+  TRACE_RESULT (current_cpu, "src2", 'x', CPU (h_gr[f_r2]));
 SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, OPRND (src2)));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2777,25 +2726,29 @@ SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform st-minus: st $src1,@-$src2.  */
 CIA
 SEM_FN_NAME (m32rx,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_17_cmp.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_17_CMP_CODE
+
 do {
   CPU (h_gr[f_r2]) = SUBSI (OPRND (src2), 4);
-  TRACE_RESULT (current_cpu, "src2", 'x', OPRND (src2));
+  TRACE_RESULT (current_cpu, "src2", 'x', CPU (h_gr[f_r2]));
 SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
-  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, OPRND (src2)));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2803,21 +2756,25 @@ SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform sub: sub $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
   CPU (h_gr[f_r1]) = SUBSI (OPRND (dr), OPRND (sr));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2826,28 +2783,32 @@ SEM_FN_NAME (m32rx,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform subv: subv $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_0_add.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_0_ADD_CODE
+
 do {
   BI temp1;SI temp0;
   temp0 = SUBSI (OPRND (dr), OPRND (sr));
   temp1 = SUBOFSI (OPRND (dr), OPRND (sr), 0);
   CPU (h_gr[f_r1]) = temp0;
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
   CPU (h_cond) = temp1;
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2856,28 +2817,32 @@ do {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform subx: subx $dr,$sr.  */
 CIA
 SEM_FN_NAME (m32rx,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_6_addx.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_6_addx.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_6_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_6_ADDX_CODE
+
 do {
   BI temp1;SI temp0;
   temp0 = SUBCSI (OPRND (dr), OPRND (sr), OPRND (condbit));
   temp1 = SUBCFSI (OPRND (dr), OPRND (sr), OPRND (condbit));
   CPU (h_gr[f_r1]) = temp0;
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
   CPU (h_cond) = temp1;
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2886,41 +2851,49 @@ do {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform trap: trap #$uimm4.  */
 CIA
 SEM_FN_NAME (m32rx,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_50_trap.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_50_trap.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_47_trap.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
+  EXTRACT_FMT_47_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
+  EXTRACT_FMT_47_TRAP_CODE
+
 do_trap (current_cpu, OPRND (uimm4));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform unlock: unlock $src1,@$src2.  */
 CIA
 SEM_FN_NAME (m32rx,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_17_cmp.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_17_CMP_CODE
+
 do_unlock (current_cpu, OPRND (src1), OPRND (src2));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -2928,129 +2901,157 @@ do_unlock (current_cpu, OPRND (src1), OPRND (src2));
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform satb: satb $dr,$src2.  */
 CIA
 SEM_FN_NAME (m32rx,satb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_51_satb.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_satb.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_48_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_48_SATB_CODE
+
   CPU (h_gr[f_r1]) = (GESI (OPRND (src2), 127)) ? (127) : (LESI (OPRND (src2), -128)) ? (-128) : (OPRND (src2));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
       m32rx_model_mark_set_h_gr (current_cpu, abuf);
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform sath: sath $dr,$src2.  */
 CIA
 SEM_FN_NAME (m32rx,sath) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_51_satb.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_satb.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_48_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_48_SATB_CODE
+
   CPU (h_gr[f_r1]) = (GESI (OPRND (src2), 32767)) ? (32767) : (LESI (OPRND (src2), -32768)) ? (-32768) : (OPRND (src2));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
       m32rx_model_mark_set_h_gr (current_cpu, abuf);
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform sat: sat $dr,$src2.  */
 CIA
 SEM_FN_NAME (m32rx,sat) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_51_satb.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_sat.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_49_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_49_SAT_CODE
+
   CPU (h_gr[f_r1]) = (OPRND (condbit)) ? ((LTSI (OPRND (src2), 0)) ? (2147483647) : (0x80000000)) : (OPRND (src2));
-  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
       m32rx_model_mark_set_h_gr (current_cpu, abuf);
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform pcmpbz: pcmpbz $src2.  */
 CIA
 SEM_FN_NAME (m32rx,pcmpbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_52_pcmpbz.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_52_pcmpbz.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_20_cmpz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_20_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_20_CMPZ_CODE
+
   CPU (h_cond) = (EQSI (ANDSI (OPRND (src2), 255), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 65280), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 0xff000000), 0)) ? (1) : (0);
-  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform sadd: sadd.  */
 CIA
 SEM_FN_NAME (m32rx,sadd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_53_sadd.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_53_sadd.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_50_sadd.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-m32rx_h_accums_set (current_cpu, 0, ADDDI (SRADI (OPRND (h_accums), 16), OPRND (h_accums)));
-  TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_50_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_50_SADD_CODE
+
+m32rx_h_accums_set (current_cpu, 0, ADDDI (SRADI (OPRND (h_accums_1), 16), OPRND (h_accums_0)));
+  TRACE_RESULT (current_cpu, "h-accums-0", 'D', m32rx_h_accums_get (current_cpu, 0));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform macwu1: macwu1 $src1,$src2.  */
 CIA
 SEM_FN_NAME (m32rx,macwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_54_macwu1.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_54_macwu1.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_macwu1.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums), MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535)))), 8), 8));
-  TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_51_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_51_MACWU1_CODE
+
+m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums_1), MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535)))), 8), 8));
+  TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -3058,21 +3059,25 @@ m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums), MULDI
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform msblo: msblo $src1,$src2.  */
 CIA
 SEM_FN_NAME (m32rx,msblo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_34_machi.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_52_msblo.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_52_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_52_MSBLO_CODE
+
   CPU (h_accum) = SRADI (SLLDI (SUBDI (OPRND (accum), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (OPRND (src1))), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8);
-  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+  TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -3080,21 +3085,25 @@ SEM_FN_NAME (m32rx,msblo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform mulwu1: mulwu1 $src1,$src2.  */
 CIA
 SEM_FN_NAME (m32rx,mulwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_17_cmp.f
+  insn_t insn = SEM_INSN (sem_arg);
 #define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_17_CMP_CODE
+
 m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535))), 16), 16));
-  TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums));
+  TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -3102,21 +3111,25 @@ m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)),
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform machl1: machl1 $src1,$src2.  */
 CIA
 SEM_FN_NAME (m32rx,machl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_54_macwu1.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_54_macwu1.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_macwu1.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
-m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums), SRADI (SLLDI (MULDI (EXTSIDI (SRASI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8));
-  TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums));
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_51_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_51_MACWU1_CODE
+
+m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums_1), SRADI (SLLDI (MULDI (EXTSIDI (SRASI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8));
+  TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1));
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
@@ -3124,55 +3137,63 @@ m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums), SRADI
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform sc: sc.  */
 CIA
 SEM_FN_NAME (m32rx,sc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_55_sc.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_55_sc.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_53_sc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_53_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_53_SC_CODE
+
 if (OPRND (condbit)) {
   CPU (h_abort) = 1;
-  TRACE_RESULT (current_cpu, "abort-parallel-execution", 'x', OPRND (abort_parallel_execution));
+  TRACE_RESULT (current_cpu, "abort-parallel-execution", 'x', CPU (h_abort));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* Perform snc: snc.  */
 CIA
 SEM_FN_NAME (m32rx,snc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_55_sc.f
-#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_55_sc.f
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_53_sc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_53_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_53_SC_CODE
+
 if (NOTBI (OPRND (condbit))) {
   CPU (h_abort) = 1;
-  TRACE_RESULT (current_cpu, "abort-parallel-execution", 'x', OPRND (abort_parallel_execution));
+  TRACE_RESULT (current_cpu, "abort-parallel-execution", 'x', CPU (h_abort));
 }
+
 #if WITH_PROFILE_MODEL_P
   if (PROFILE_MODEL_P (current_cpu))
     {
       m32rx_model_profile_insn (current_cpu, abuf);
     }
 #endif
+
   return new_pc;
 #undef OPRND
-#undef FLD
 }
 
 /* FIXME: Add "no return" attribute to illegal insn handlers.
diff --git a/sim/m32r/sim-main.h b/sim/m32r/sim-main.h
index c507dcc..90883b3 100644
--- a/sim/m32r/sim-main.h
+++ b/sim/m32r/sim-main.h
@@ -9,6 +9,7 @@ typedef struct _sim_cpu SIM_CPU;
    sim-basics.h and cgen-types.h needs config.h.  */
 #include "config.h"
 
+#include "ansidecl.h"
 #include "cgen-types.h"
 #include "arch.h"
 #include "sim-basics.h"
@@ -24,7 +25,6 @@ typedef SI sim_cia;
 #include "cgen-sim.h"
 /*#include "cgen-mem.h"*/
 #include "cgen-trace.h"
-#include "cpu-opc.h" /* Needed for INSN_NAME.  */
 #include "cpu-sim.h"
 
 #ifdef WANT_CPU_M32R
-- 
2.7.4