From b8701dc1749e228b886e53bdb32eeebba00e30da Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Fri, 7 May 2021 20:05:30 +0300 Subject: [PATCH] [X86] AMD Zen 3: mark XMM/YMM (but not MMX!) reg moves as eliminatible in RegisterFile --- llvm/lib/Target/X86/X86ScheduleZnver3.td | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86ScheduleZnver3.td b/llvm/lib/Target/X86/X86ScheduleZnver3.td index 21a9897..8f3d8de 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver3.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver3.td @@ -336,7 +336,9 @@ def Zn3FPCLM01 : ProcResGroup<[Zn3FPCLM0, Zn3FPCLM1]>; // The floating point register file has 160 vector registers // of 128 bits each in Zen 1 and 256 bits each in Zen 2. // anandtech also confirms this. -def Zn3FpPRF : RegisterFile<160, [VR64, VR128, VR256], [1, 1, 1]>; +def Zn3FpPRF : RegisterFile<160, [VR64, VR128, VR256], [1, 1, 1], [0, 1, 1], + 6, // Max moves that can be eliminated per cycle. + 0>; // Restrict move elimination to zero regs. // AMD SOG 19h, 2.11 Floating-Point Unit // The floating-point scheduler has a 2*32 entry macro op capacity. -- 2.7.4