From b8283631a53e800bf8a029901de2ac8a5aa739e9 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 1 Apr 2016 17:55:02 +0000 Subject: [PATCH] [X86][SSE] Regenerated vec_setcc tests. llvm-svn: 265164 --- llvm/test/CodeGen/X86/vec_setcc.ll | 242 ++++++++++++++++++++----------------- 1 file changed, 131 insertions(+), 111 deletions(-) diff --git a/llvm/test/CodeGen/X86/vec_setcc.ll b/llvm/test/CodeGen/X86/vec_setcc.ll index b69f90c..1eef0be 100644 --- a/llvm/test/CodeGen/X86/vec_setcc.ll +++ b/llvm/test/CodeGen/X86/vec_setcc.ll @@ -1,179 +1,199 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse2 | FileCheck %s -check-prefix=SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse4.1 | FileCheck %s -check-prefix=SSE41 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx | FileCheck %s -check-prefix=AVX +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX define <16 x i8> @v16i8_icmp_uge(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable { +; SSE-LABEL: v16i8_icmp_uge: +; SSE: # BB#0: +; SSE-NEXT: pmaxub %xmm0, %xmm1 +; SSE-NEXT: pcmpeqb %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: v16i8_icmp_uge: +; AVX: # BB#0: +; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq %1 = icmp uge <16 x i8> %a, %b %2 = sext <16 x i1> %1 to <16 x i8> ret <16 x i8> %2 -; SSE2-LABEL: v16i8_icmp_uge: -; SSE2: pmaxub %xmm0, %xmm1 -; SSE2: pcmpeqb %xmm1, %xmm0 - -; SSE41-LABEL: v16i8_icmp_uge: -; SSE41: pmaxub %xmm0, %xmm1 -; SSE41: pcmpeqb %xmm1, %xmm0 - -; AVX-LABEL: v16i8_icmp_uge: -; AVX: vpmaxub %xmm1, %xmm0, %xmm1 -; AVX: vpcmpeqb %xmm1, %xmm0, %xmm0 } define <16 x i8> @v16i8_icmp_ule(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable { +; SSE-LABEL: v16i8_icmp_ule: +; SSE: # BB#0: +; SSE-NEXT: pminub %xmm0, %xmm1 +; SSE-NEXT: pcmpeqb %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: v16i8_icmp_ule: +; AVX: # BB#0: +; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq %1 = icmp ule <16 x i8> %a, %b %2 = sext <16 x i1> %1 to <16 x i8> ret <16 x i8> %2 -; SSE2-LABEL: v16i8_icmp_ule: -; SSE2: pminub %xmm0, %xmm1 -; SSE2: pcmpeqb %xmm1, %xmm0 - -; SSE41-LABEL: v16i8_icmp_ule: -; SSE41: pminub %xmm0, %xmm1 -; SSE41: pcmpeqb %xmm1, %xmm0 - -; AVX-LABEL: v16i8_icmp_ule: -; AVX: vpminub %xmm1, %xmm0, %xmm1 -; AVX: vpcmpeqb %xmm1, %xmm0, %xmm0 } - define <8 x i16> @v8i16_icmp_uge(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable { - %1 = icmp uge <8 x i16> %a, %b - %2 = sext <8 x i1> %1 to <8 x i16> - ret <8 x i16> %2 ; SSE2-LABEL: v8i16_icmp_uge: -; SSE2: psubusw %xmm0, %xmm1 -; SEE2: pxor %xmm0, %xmm0 -; SSE2: pcmpeqw %xmm1, %xmm0 - +; SSE2: # BB#0: +; SSE2-NEXT: psubusw %xmm0, %xmm1 +; SSE2-NEXT: pxor %xmm0, %xmm0 +; SSE2-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE2-NEXT: retq +; ; SSE41-LABEL: v8i16_icmp_uge: -; SSE41: pmaxuw %xmm0, %xmm1 -; SSE41: pcmpeqw %xmm1, %xmm0 - +; SSE41: # BB#0: +; SSE41-NEXT: pmaxuw %xmm0, %xmm1 +; SSE41-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE41-NEXT: retq +; ; AVX-LABEL: v8i16_icmp_uge: -; AVX: vpmaxuw %xmm1, %xmm0, %xmm1 -; AVX: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX: # BB#0: +; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %1 = icmp uge <8 x i16> %a, %b + %2 = sext <8 x i1> %1 to <8 x i16> + ret <8 x i16> %2 } define <8 x i16> @v8i16_icmp_ule(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable { - %1 = icmp ule <8 x i16> %a, %b - %2 = sext <8 x i1> %1 to <8 x i16> - ret <8 x i16> %2 ; SSE2-LABEL: v8i16_icmp_ule: -; SSE2: psubusw %xmm1, %xmm0 -; SSE2: pxor %xmm1, %xmm1 -; SSE2: pcmpeqw %xmm1, %xmm0 - +; SSE2: # BB#0: +; SSE2-NEXT: psubusw %xmm1, %xmm0 +; SSE2-NEXT: pxor %xmm1, %xmm1 +; SSE2-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE2-NEXT: retq +; ; SSE41-LABEL: v8i16_icmp_ule: -; SSE41: pminuw %xmm0, %xmm1 -; SSE41: pcmpeqw %xmm1, %xmm0 - +; SSE41: # BB#0: +; SSE41-NEXT: pminuw %xmm0, %xmm1 +; SSE41-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE41-NEXT: retq +; ; AVX-LABEL: v8i16_icmp_ule: -; AVX: vpminuw %xmm1, %xmm0, %xmm1 -; AVX: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX: # BB#0: +; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %1 = icmp ule <8 x i16> %a, %b + %2 = sext <8 x i1> %1 to <8 x i16> + ret <8 x i16> %2 } - define <4 x i32> @v4i32_icmp_uge(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable { - %1 = icmp uge <4 x i32> %a, %b - %2 = sext <4 x i1> %1 to <4 x i32> - ret <4 x i32> %2 ; SSE2-LABEL: v4i32_icmp_uge: -; SSE2: movdqa {{.*}}(%rip), %xmm2 -; SSE2: pxor %xmm2, %xmm0 -; SSE2: pxor %xmm1, %xmm2 -; SSE2: pcmpgtd %xmm0, %xmm2 -; SSE2: pcmpeqd %xmm0, %xmm0 -; SSE2: pxor %xmm2, %xmm0 - +; SSE2: # BB#0: +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; SSE2-NEXT: pxor %xmm2, %xmm0 +; SSE2-NEXT: pxor %xmm1, %xmm2 +; SSE2-NEXT: pcmpgtd %xmm0, %xmm2 +; SSE2-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE2-NEXT: pxor %xmm2, %xmm0 +; SSE2-NEXT: retq +; ; SSE41-LABEL: v4i32_icmp_uge: -; SSE41: pmaxud %xmm0, %xmm1 -; SSE41: pcmpeqd %xmm1, %xmm0 - +; SSE41: # BB#0: +; SSE41-NEXT: pmaxud %xmm0, %xmm1 +; SSE41-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE41-NEXT: retq +; ; AVX-LABEL: v4i32_icmp_uge: -; AVX: vpmaxud %xmm1, %xmm0, %xmm1 -; AVX: vpcmpeqd %xmm1, %xmm0, %xmm0 +; AVX: # BB#0: +; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %1 = icmp uge <4 x i32> %a, %b + %2 = sext <4 x i1> %1 to <4 x i32> + ret <4 x i32> %2 } define <4 x i32> @v4i32_icmp_ule(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable { - %1 = icmp ule <4 x i32> %a, %b - %2 = sext <4 x i1> %1 to <4 x i32> - ret <4 x i32> %2 ; SSE2-LABEL: v4i32_icmp_ule: -; SSE2: movdqa {{.*}}(%rip), %xmm2 -; SSE2: pxor %xmm2, %xmm1 -; SSE2: pxor %xmm2, %xmm0 -; SSE2: pcmpgtd %xmm1, %xmm0 -; SSE2: pcmpeqd %xmm1, %xmm1 -; SSE2: pxor %xmm1, %xmm0 - +; SSE2: # BB#0: +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; SSE2-NEXT: pxor %xmm2, %xmm1 +; SSE2-NEXT: pxor %xmm2, %xmm0 +; SSE2-NEXT: pcmpgtd %xmm1, %xmm0 +; SSE2-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE2-NEXT: pxor %xmm1, %xmm0 +; SSE2-NEXT: retq +; ; SSE41-LABEL: v4i32_icmp_ule: -; SSE41: pminud %xmm0, %xmm1 -; SSE41: pcmpeqd %xmm1, %xmm0 - +; SSE41: # BB#0: +; SSE41-NEXT: pminud %xmm0, %xmm1 +; SSE41-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE41-NEXT: retq +; ; AVX-LABEL: v4i32_icmp_ule: -; AVX: pminud %xmm1, %xmm0, %xmm1 -; AVX: pcmpeqd %xmm1, %xmm0, %xmm0 +; AVX: # BB#0: +; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %1 = icmp ule <4 x i32> %a, %b + %2 = sext <4 x i1> %1 to <4 x i32> + ret <4 x i32> %2 } ; At one point we were incorrectly constant-folding a setcc to 0x1 instead of ; 0xff, leading to a constpool load. The instruction doesn't matter here, but it ; should set all bits to 1. define <16 x i8> @test_setcc_constfold_vi8(<16 x i8> %l, <16 x i8> %r) { +; SSE-LABEL: test_setcc_constfold_vi8: +; SSE: # BB#0: +; SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: test_setcc_constfold_vi8: +; AVX: # BB#0: +; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX-NEXT: retq %test1 = icmp eq <16 x i8> %l, %r %mask1 = sext <16 x i1> %test1 to <16 x i8> - %test2 = icmp ne <16 x i8> %l, %r %mask2 = sext <16 x i1> %test2 to <16 x i8> - %res = or <16 x i8> %mask1, %mask2 ret <16 x i8> %res -; SSE2-LABEL: test_setcc_constfold_vi8: -; SSE2: pcmpeqd %xmm0, %xmm0 - -; SSE41-LABEL: test_setcc_constfold_vi8: -; SSE41: pcmpeqd %xmm0, %xmm0 - -; AVX-LABEL: test_setcc_constfold_vi8: -; AVX: vpcmpeqd %xmm0, %xmm0, %xmm0 } ; Make sure sensible results come from doing extension afterwards define <16 x i8> @test_setcc_constfold_vi1(<16 x i8> %l, <16 x i8> %r) { +; SSE-LABEL: test_setcc_constfold_vi1: +; SSE: # BB#0: +; SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: test_setcc_constfold_vi1: +; AVX: # BB#0: +; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX-NEXT: retq %test1 = icmp eq <16 x i8> %l, %r %test2 = icmp ne <16 x i8> %l, %r - %res = or <16 x i1> %test1, %test2 %mask = sext <16 x i1> %res to <16 x i8> ret <16 x i8> %mask -; SSE2-LABEL: test_setcc_constfold_vi1: -; SSE2: pcmpeqd %xmm0, %xmm0 - -; SSE41-LABEL: test_setcc_constfold_vi1: -; SSE41: pcmpeqd %xmm0, %xmm0 - -; AVX-LABEL: test_setcc_constfold_vi1: -; AVX: vpcmpeqd %xmm0, %xmm0, %xmm0 } - ; 64-bit case is also particularly important, as the constant "-1" is probably ; just 32-bits wide. define <2 x i64> @test_setcc_constfold_vi64(<2 x i64> %l, <2 x i64> %r) { +; SSE-LABEL: test_setcc_constfold_vi64: +; SSE: # BB#0: +; SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: test_setcc_constfold_vi64: +; AVX: # BB#0: +; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX-NEXT: retq %test1 = icmp eq <2 x i64> %l, %r %mask1 = sext <2 x i1> %test1 to <2 x i64> - %test2 = icmp ne <2 x i64> %l, %r %mask2 = sext <2 x i1> %test2 to <2 x i64> - %res = or <2 x i64> %mask1, %mask2 ret <2 x i64> %res -; SSE2-LABEL: test_setcc_constfold_vi64: -; SSE2: pcmpeqd %xmm0, %xmm0 - -; SSE41-LABEL: test_setcc_constfold_vi64: -; SSE41: pcmpeqd %xmm0, %xmm0 - -; AVX-LABEL: test_setcc_constfold_vi64: -; AVX: vpcmpeqd %xmm0, %xmm0, %xmm0 } -- 2.7.4