From b81fdb5a14398ef5f9a1a2e7a1d93ac6878854b4 Mon Sep 17 00:00:00 2001 From: Diego Novillo Date: Tue, 5 Oct 1999 12:18:56 +0000 Subject: [PATCH] mips.c (mips_move_2words): Split doubles if ISA >= 3, !TARGET_64BIT, and destination is not an FP register. * config/mips/mips.c (mips_move_2words): Split doubles if ISA >= 3, !TARGET_64BIT, and destination is not an FP register. Co-Authored-By: Jonathan Larmour From-SVN: r29824 --- gcc/ChangeLog | 6 ++++++ gcc/config/mips/mips.c | 12 +++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c94f985..5f257ccf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +Mon Oct 4 16:48:16 1999 Diego Novillo + Jonathan Larmour + + * config/mips/mips.c (mips_move_2words): Split doubles if + ISA >= 3, !TARGET_64BIT, and destination is not an FP register. + Mon Oct 4 21:47:31 1999 Richard Henderson * genrecog.c (struct decision_test): New. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index f24452b..b760292 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -2214,7 +2214,17 @@ mips_move_2words (operands, insn) } else #endif - ret = "li.d\t%0,%1"; + /* GNU as emits 64-bit code for li.d if the ISA is 3 + or higher. For !TARGET_64BIT && gp registers we + need to avoid this by using two li instructions + instead. */ + if (mips_isa >= 3 && !TARGET_64BIT && !FP_REG_P (regno0)) + { + split_double (op1, operands + 2, operands + 3); + ret = "li\t%0,%2\n\tli\t%D0,%3"; + } + else + ret = "li.d\t%0,%1"; } else if (TARGET_64BIT) -- 2.7.4