From b7baa358f632324f593deeba3daa3268795bd258 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 8 Apr 2018 17:53:18 +0000 Subject: [PATCH] [X86] Add SchedWrites for CMOV and SETCC. Use them to remove InstRWs. Summary: Cmov and setcc previously used WriteALU, but on Intel processors at least they are more restricted than basic ALU ops. This patch adds new SchedWrites for them and removes the InstRWs. I had to leave some InstRWs for CMOVA/CMOVBE and SETA/SETBE because those have an extra uop relative to the other condition codes on Intel CPUs. The test changes are due to fixing a missing ZnAGU dependency on the memory form of setcc. Reviewers: RKSimon, andreadb, GGanesh Reviewed By: RKSimon Subscribers: GGanesh, llvm-commits Differential Revision: https://reviews.llvm.org/D45380 llvm-svn: 329539 --- llvm/lib/Target/X86/X86InstrCMovSetCC.td | 8 +++---- llvm/lib/Target/X86/X86SchedBroadwell.td | 17 ++++++--------- llvm/lib/Target/X86/X86SchedHaswell.td | 17 ++++++--------- llvm/lib/Target/X86/X86SchedSandyBridge.td | 17 ++++++--------- llvm/lib/Target/X86/X86SchedSkylakeClient.td | 17 ++++++--------- llvm/lib/Target/X86/X86SchedSkylakeServer.td | 17 ++++++--------- llvm/lib/Target/X86/X86Schedule.td | 15 +++++++------ llvm/lib/Target/X86/X86ScheduleBtVer2.td | 4 ++++ llvm/lib/Target/X86/X86ScheduleSLM.td | 7 ++++++ llvm/lib/Target/X86/X86ScheduleZnver1.td | 20 ++++------------- llvm/test/CodeGen/X86/schedule-x86_64.ll | 32 ++++++++++++++-------------- 11 files changed, 79 insertions(+), 92 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td index 163e68a..425b25a 100644 --- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td +++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td @@ -16,7 +16,7 @@ // CMOV instructions. multiclass CMOV opc, string Mnemonic, PatLeaf CondNode> { let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", - isCommutable = 1, SchedRW = [WriteALU] in { + isCommutable = 1, SchedRW = [WriteCMOV] in { def NAME#16rr : I opc, string Mnemonic, PatLeaf CondNode> { } let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", - SchedRW = [WriteALULd, ReadAfterLd] in { + SchedRW = [WriteCMOVLd, ReadAfterLd] in { def NAME#16rm : I opc, string Mnemonic, PatLeaf OpNode> { def r : I, TB, Sched<[WriteALU]>; + IIC_SET_R>, TB, Sched<[WriteSETCC]>; def m : I, TB, Sched<[WriteALU, WriteStore]>; + IIC_SET_M>, TB, Sched<[WriteSETCCStore]>; } // Uses = [EFLAGS] } diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 589d878..fb53087 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -113,6 +113,13 @@ def : WriteRes { let Latency = 3; } // Integer multiplication, h def : WriteRes; // LEA instructions can't fold loads. +defm : BWWriteResPair; // Conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + // Bit counts. defm : BWWriteResPair; defm : BWWriteResPair; @@ -469,7 +476,6 @@ def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri", "BTR(16|32|64)rr", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4", "JMP_1", @@ -481,7 +487,6 @@ def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri", "SBB(16|32|64)ri", "SBB(16|32|64)i", "SBB(8|16|32|64)rr", - "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", "SHLX(32|64)rr", @@ -791,13 +796,6 @@ def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> { } def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>; -def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>; - def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> { let Latency = 2; let NumMicroOps = 3; @@ -1398,7 +1396,6 @@ def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> { let ResourceCycles = [1,1]; } def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm", "RORX(32|64)mi", "SARX(32|64)rm", "SHLX(32|64)rm", diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 544bb65..29f120f 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -119,6 +119,13 @@ defm : HWWriteResPair; defm : HWWriteResPair; defm : HWWriteResPair; +defm : HWWriteResPair; // Conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + // This is for simple LEAs with one or two input operands. // The complex ones can only execute on port 1, and they require two cycles on // the port to read all inputs. We don't model that. @@ -830,7 +837,6 @@ def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8", "SAR(8|16|32|64)r1", "SAR(8|16|32|64)ri", "SARX(32|64)rr", - "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", "SHLX(32|64)rr", @@ -1405,13 +1411,6 @@ def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> { } def: InstRW<[HWWriteResGroup21], (instregex "FNSTCW16m")>; -def HWWriteResGroup22 : SchedWriteRes<[HWPort4,HWPort237,HWPort06]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[HWWriteResGroup22], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>; - def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> { let Latency = 2; let NumMicroOps = 3; @@ -1568,7 +1567,6 @@ def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>; def: InstRW<[HWWriteResGroup35], (instregex "ADC(8|16|32|64)ri", "ADC(8|16|32|64)rr", "ADC(8|16|32|64)i", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "SBB(8|16|32|64)ri", "SBB(8|16|32|64)rr", "SBB(8|16|32|64)i", @@ -1663,7 +1661,6 @@ def HWWriteResGroup43 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[HWWriteResGroup43], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>; def: InstRW<[HWWriteResGroup43, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm, SBB8rm, SBB16rm, SBB32rm, SBB64rm)>; diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 00e1441..5a2121f 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -110,6 +110,13 @@ defm : SBWriteResPair; defm : SBWriteResPair; defm : SBWriteResPair; +defm : SBWriteResPair; // Conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + // This is for simple LEAs with one or two input operands. // The complex ones can only execute on port 1, and they require two cycles on // the port to read all inputs. We don't model that. @@ -382,7 +389,6 @@ def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8", "SAHF", "SAR(8|16|32|64)ri", "SAR(8|16|32|64)r1", - "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r", "SHL(8|16|32|64)ri", "SHL(8|16|32|64)r1", "SHR(8|16|32|64)ri", @@ -624,7 +630,6 @@ def SBWriteResGroup19 : SchedWriteRes<[SBPort05,SBPort015]> { def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)ri", "ADC(8|16|32|64)rr", "ADC(8|16|32|64)i", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "SBB(8|16|32|64)ri", "SBB(8|16|32|64)rr", "SBB(8|16|32|64)i", @@ -949,13 +954,6 @@ def SBWriteResGroup37 : SchedWriteRes<[SBPort4,SBPort01,SBPort23]> { def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPD(Y?)mr", "VMASKMOVPS(Y?)mr")>; -def SBWriteResGroup38 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup38], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>; - def SBWriteResGroup39 : SchedWriteRes<[SBPort4,SBPort23,SBPort15]> { let Latency = 5; let NumMicroOps = 3; @@ -1297,7 +1295,6 @@ def SBWriteResGroup65 : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SBWriteResGroup65], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>; def: InstRW<[SBWriteResGroup65, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm, SBB8rm, SBB16rm, SBB32rm, SBB64rm)>; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 9314f85..59e05df 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -113,6 +113,13 @@ defm : SKLWriteResPair; def : WriteRes { let Latency = 3; } // Integer multiplication, high part. def : WriteRes; // LEA instructions can't fold loads. +defm : SKLWriteResPair; // Conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + // Bit counts. defm : SKLWriteResPair; defm : SKLWriteResPair; @@ -534,7 +541,6 @@ def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", "CLAC", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4", "JMP_1", @@ -546,7 +552,6 @@ def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri", "SBB(16|32|64)ri", "SBB(16|32|64)i", "SBB(8|16|32|64)rr", - "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", "SHLX(32|64)rr", @@ -812,13 +817,6 @@ def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> { } def: InstRW<[SKLWriteResGroup25], (instregex "FNSTCW16m")>; -def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SKLWriteResGroup26], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>; - def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> { let Latency = 2; let NumMicroOps = 3; @@ -1421,7 +1419,6 @@ def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> { let ResourceCycles = [1,1]; } def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm", "RORX(32|64)mi", "SARX(32|64)rm", "SHLX(32|64)rm", diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index fe14400..c7c7e2a 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -113,6 +113,13 @@ defm : SKXWriteResPair; def : WriteRes { let Latency = 3; } // Integer multiplication, high part. def : WriteRes; // LEA instructions can't fold loads. +defm : SKXWriteResPair; // Conditional move. +def : WriteRes; // Setcc. +def : WriteRes { + let Latency = 2; + let NumMicroOps = 3; +} + // Integer shifts and rotates. defm : SKXWriteResPair; @@ -1010,7 +1017,6 @@ def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", "CLAC", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1", "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4", "JMP_1", @@ -1022,7 +1028,6 @@ def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri", "SBB(16|32|64)ri", "SBB(16|32|64)i", "SBB(8|16|32|64)rr", - "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", "SHLX(32|64)rr", @@ -1617,13 +1622,6 @@ def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> { } def: InstRW<[SKXWriteResGroup25], (instregex "FNSTCW16m")>; -def SKXWriteResGroup26 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SKXWriteResGroup26], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>; - def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { let Latency = 2; let NumMicroOps = 3; @@ -3050,7 +3048,6 @@ def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> { let ResourceCycles = [1,1]; } def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8", - "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm", "RORX(32|64)mi", "SARX(32|64)rm", "SHLX(32|64)rm", diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index 8dc2eac..7f381a8 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -39,9 +39,14 @@ multiclass X86SchedWritePair { } } +// Loads, stores, and moves, not folded with other operations. +def WriteLoad : SchedWrite; +def WriteStore : SchedWrite; +def WriteMove : SchedWrite; + // Arithmetic. defm WriteALU : X86SchedWritePair; // Simple integer ALU op. -def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>; +def WriteALURMW : WriteSequence<[WriteALULd, WriteStore]>; defm WriteIMul : X86SchedWritePair; // Integer multiplication. def WriteIMulH : SchedWrite; // Integer multiplication, high part. defm WriteIDiv : X86SchedWritePair; // Integer division. @@ -51,6 +56,9 @@ defm WriteBitScan : X86SchedWritePair; // Bit scan forward/reverse. defm WritePOPCNT : X86SchedWritePair; // Bit population count. defm WriteLZCNT : X86SchedWritePair; // Leading zero count. defm WriteTZCNT : X86SchedWritePair; // Trailing zero count. +defm WriteCMOV : X86SchedWritePair; // Conditional move. +def WriteSETCC : SchedWrite; // Set register based on condition code. +def WriteSETCCStore : SchedWrite; // Integer shifts and rotates. defm WriteShift : X86SchedWritePair; @@ -59,11 +67,6 @@ defm WriteShift : X86SchedWritePair; defm WriteBEXTR : X86SchedWritePair; defm WriteBZHI : X86SchedWritePair; -// Loads, stores, and moves, not folded with other operations. -def WriteLoad : SchedWrite; -def WriteStore : SchedWrite; -def WriteMove : SchedWrite; - // Idioms that clear a register, like xorps %xmm0, %xmm0. // These can often bypass execution ports completely. def WriteZero : SchedWrite; diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 637dd4d..f9dfefb 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -141,6 +141,10 @@ defm : JWriteResIntPair; // i8/i16/i32 defm : JWriteResIntPair; // Worst case (i64 division) defm : JWriteResIntPair; +defm : JWriteResIntPair; // Conditional move. +def : WriteRes; // Setcc. +def : WriteRes; + def : WriteRes { let Latency = 6; let ResourceCycles = [4]; diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td index 5357e6a..73eb257 100644 --- a/llvm/lib/Target/X86/X86ScheduleSLM.td +++ b/llvm/lib/Target/X86/X86ScheduleSLM.td @@ -93,6 +93,13 @@ defm : SLMWriteResPair; defm : SLMWriteResPair; defm : SLMWriteResPair; +defm : SLMWriteResPair; +def : WriteRes; +def : WriteRes { + // FIXME Latency and NumMicrOps? + let ResourceCycles = [2,1]; +} + // This is for simple LEAs with one or two input operands. // The complex ones can only execute on port 1, and they require two cycles on // the port to read all inputs. We don't model that. diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index 834a254..3018e0f 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -153,6 +153,10 @@ defm : ZnWriteResPair; defm : ZnWriteResPair; defm : ZnWriteResFpuPair; +defm : ZnWriteResPair; +def : WriteRes; +def : WriteRes; + // Bit counts. defm : ZnWriteResPair; defm : ZnWriteResPair; @@ -277,14 +281,6 @@ def : InstRW<[WriteALULd, ReadAfterLd], (instregex "MOV16rm")>; // r,m. def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>; -// CMOVcc. -// r,r. -def : InstRW<[WriteALU], - (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>; -// r,m. -def : InstRW<[WriteALULd, ReadAfterLd], - (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>; - // XCHG. // r,r. def ZnWriteXCHG : SchedWriteRes<[ZnALU]> { @@ -614,14 +610,6 @@ def : InstRW<[WriteMicrocoded], (instregex "SHRD(16|32|64)rrCL")>; // m,r,cl. def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>; -// SETcc. -// r. -def : InstRW<[WriteShift], - (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)r")>; -// m. -def : InstRW<[WriteShift], - (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)m")>; - //-- Misc instructions --// // CMPXCHG. def ZnWriteCMPXCHG : SchedWriteRes<[ZnAGU, ZnALU]> { diff --git a/llvm/test/CodeGen/X86/schedule-x86_64.ll b/llvm/test/CodeGen/X86/schedule-x86_64.ll index c1019e4..105e660 100644 --- a/llvm/test/CodeGen/X86/schedule-x86_64.ll +++ b/llvm/test/CodeGen/X86/schedule-x86_64.ll @@ -13882,22 +13882,22 @@ define void @test_setcc(i8 %a0, i8 *%a1) optsize { ; ZNVER1-NEXT: setge %dil # sched: [1:0.25] ; ZNVER1-NEXT: setle %dil # sched: [1:0.25] ; ZNVER1-NEXT: setg %dil # sched: [1:0.25] -; ZNVER1-NEXT: seto (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setno (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setb (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setae (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: sete (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setne (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setbe (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: seta (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: sets (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setns (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setp (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setnp (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setl (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setge (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setle (%rsi) # sched: [1:0.25] -; ZNVER1-NEXT: setg (%rsi) # sched: [1:0.25] +; ZNVER1-NEXT: seto (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setno (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setb (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setae (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: sete (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setne (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setbe (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: seta (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: sets (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setns (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setp (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setnp (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setl (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setge (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setle (%rsi) # sched: [1:0.50] +; ZNVER1-NEXT: setg (%rsi) # sched: [1:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retq # sched: [1:0.50] call void asm sideeffect "seto $0 \0A\09 setno $0 \0A\09 setb $0 \0A\09 setnb $0 \0A\09 setz $0 \0A\09 setnz $0 \0A\09 setbe $0 \0A\09 setnbe $0 \0A\09 sets $0 \0A\09 setns $0 \0A\09 setp $0 \0A\09 setnp $0 \0A\09 setl $0 \0A\09 setnl $0 \0A\09 setle $0 \0A\09 setnle $0 \0A\09 seto $1 \0A\09 setno $1 \0A\09 setb $1 \0A\09 setnb $1 \0A\09 setz $1 \0A\09 setnz $1 \0A\09 setbe $1 \0A\09 setnbe $1 \0A\09 sets $1 \0A\09 setns $1 \0A\09 setp $1 \0A\09 setnp $1 \0A\09 setl $1 \0A\09 setnl $1 \0A\09 setle $1 \0A\09 setnle $1", "r,*m"(i8 %a0, i8 *%a1) -- 2.7.4