From b7795fb143c2dfd5757f3949faeb07fedf676e0b Mon Sep 17 00:00:00 2001 From: Ju-Zhe Zhong Date: Fri, 10 Feb 2023 14:46:34 +0800 Subject: [PATCH] RISC-V: Add vssrl.vx C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vssrl_vx-1.C: New test. * g++.target/riscv/rvv/base/vssrl_vx-2.C: New test. * g++.target/riscv/rvv/base/vssrl_vx-3.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vssrl_vx-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C | 160 +++++++++++ 15 files changed, 2862 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-1.C new file mode 100644 index 0000000..2a3d21a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-1.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl(vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl(vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl(vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl(vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl(vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl(vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl(vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vssrl(vbool64_t mask,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl(vbool32_t mask,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl(vbool16_t mask,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl(vbool8_t mask,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl(vbool4_t mask,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl(vbool2_t mask,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl(vbool1_t mask,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-2.C new file mode 100644 index 0000000..d132757 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-2.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl(vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl(vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl(vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl(vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl(vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl(vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl(vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,31); +} + + +vuint8mf8_t test___riscv_vssrl(vbool64_t mask,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl(vbool32_t mask,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl(vbool16_t mask,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl(vbool8_t mask,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl(vbool4_t mask,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl(vbool2_t mask,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl(vbool1_t mask,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-3.C new file mode 100644 index 0000000..2bf17af --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-3.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl(vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl(vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl(vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl(vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl(vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl(vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl(vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(op1,shift,32); +} + + +vuint8mf8_t test___riscv_vssrl(vbool64_t mask,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl(vbool32_t mask,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl(vbool16_t mask,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl(vbool8_t mask,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl(vbool4_t mask,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl(vbool2_t mask,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl(vbool1_t mask,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-1.C new file mode 100644 index 0000000..770c1e9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-2.C new file mode 100644 index 0000000..9b3884d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-3.C new file mode 100644 index 0000000..59deaa3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-1.C new file mode 100644 index 0000000..b5b5000 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_tu(vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl_tu(vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl_tu(vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl_tu(vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl_tu(vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl_tu(vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl_tu(vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl_tu(vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl_tu(vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl_tu(vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl_tu(vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl_tu(vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl_tu(vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl_tu(vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl_tu(vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl_tu(vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl_tu(vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl_tu(vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl_tu(vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl_tu(vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl_tu(vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl_tu(vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-2.C new file mode 100644 index 0000000..9dfe241 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_tu(vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl_tu(vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl_tu(vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl_tu(vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl_tu(vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl_tu(vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl_tu(vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl_tu(vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl_tu(vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl_tu(vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl_tu(vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl_tu(vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl_tu(vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl_tu(vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl_tu(vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl_tu(vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl_tu(vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl_tu(vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl_tu(vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl_tu(vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl_tu(vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl_tu(vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-3.C new file mode 100644 index 0000000..202b2c8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_tu(vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl_tu(vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl_tu(vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl_tu(vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl_tu(vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl_tu(vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl_tu(vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl_tu(vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl_tu(vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl_tu(vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl_tu(vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl_tu(vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl_tu(vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl_tu(vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl_tu(vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl_tu(vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl_tu(vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl_tu(vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl_tu(vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl_tu(vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl_tu(vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl_tu(vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-1.C new file mode 100644 index 0000000..09b3806 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-2.C new file mode 100644 index 0000000..2cf634b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-3.C new file mode 100644 index 0000000..30bd81c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C new file mode 100644 index 0000000..7e3c715 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vssrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vssrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vssrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vssrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vssrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vssrl_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vssrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vssrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vssrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vssrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vssrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vssrl_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vssrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vssrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vssrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vssrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vssrl_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vssrl_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vssrl_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vssrl_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vssrl_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C new file mode 100644 index 0000000..8002e78 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vssrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vssrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vssrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vssrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vssrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vssrl_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vssrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vssrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vssrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vssrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vssrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vssrl_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vssrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vssrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vssrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vssrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vssrl_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vssrl_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vssrl_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vssrl_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vssrl_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C new file mode 100644 index 0000000..7ce05a9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vssrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vssrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vssrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vssrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vssrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vssrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vssrl_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vssrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vssrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vssrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vssrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vssrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vssrl_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vssrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vssrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vssrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vssrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vssrl_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vssrl_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vssrl_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vssrl_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vssrl_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vssrl_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ -- 2.7.4