From b7249bf3b5f56fcd9349b862be5aa669679998e4 Mon Sep 17 00:00:00 2001
From: Ben Shi <powerman1st@163.com>
Date: Tue, 20 Apr 2021 12:11:56 +0800
Subject: [PATCH] [RISCV][test] Add a new test of addition

Reviewed by: craig.topper

Differential Revision: https://reviews.llvm.org/D100767
---
 llvm/test/CodeGen/RISCV/add-imm.ll | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/llvm/test/CodeGen/RISCV/add-imm.ll b/llvm/test/CodeGen/RISCV/add-imm.ll
index 2db13eb..548a2e2 100644
--- a/llvm/test/CodeGen/RISCV/add-imm.ll
+++ b/llvm/test/CodeGen/RISCV/add-imm.ll
@@ -150,6 +150,23 @@ define i32 @add32_accept(i32 %a) nounwind {
   ret i32 %1
 }
 
+define signext i32 @add32_sext_accept(i32 signext %a) nounwind {
+; RV32I-LABEL: add32_sext_accept:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 1500
+; RV32I-NEXT:    addi a0, a0, 1499
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add32_sext_accept:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, -1097
+; RV64I-NEXT:    addw a0, a0, a1
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, 2999
+  ret i32 %1
+}
+
 define i64 @add64_accept(i64 %a) nounwind {
 ; RV32I-LABEL: add64_accept:
 ; RV32I:       # %bb.0:
-- 
2.7.4