From b688a6d2277ddd7f2a57a6cc772c8fc3968b09d7 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Timur=20Krist=C3=B3f?= Date: Tue, 28 Mar 2023 01:35:08 +0200 Subject: [PATCH] nir: Remove IB address and stride intrinsics. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit RADV used these to emulate firstTask for NV_mesh_shader. They are no longer needed. Signed-off-by: Timur Kristóf Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_nir_lower_abi.c | 6 ------ src/compiler/nir/nir_divergence_analysis.c | 2 -- src/compiler/nir/nir_intrinsics.py | 3 --- 3 files changed, 11 deletions(-) diff --git a/src/amd/vulkan/radv_nir_lower_abi.c b/src/amd/vulkan/radv_nir_lower_abi.c index 95a79c0..ea6484f 100644 --- a/src/amd/vulkan/radv_nir_lower_abi.c +++ b/src/amd/vulkan/radv_nir_lower_abi.c @@ -272,12 +272,6 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state) case nir_intrinsic_load_task_ring_entry_amd: replacement = ac_nir_load_arg(b, &s->args->ac, s->args->ac.task_ring_entry); break; - case nir_intrinsic_load_task_ib_addr: - replacement = nir_imm_zero(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size); - break; - case nir_intrinsic_load_task_ib_stride: - replacement = nir_imm_zero(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size); - break; case nir_intrinsic_load_lshs_vertex_stride_amd: { unsigned io_num = stage == MESA_SHADER_VERTEX ? s->info->vs.num_linked_outputs : diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index ab6286f..e70d1a8 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -162,8 +162,6 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_streamout_write_index_amd: case nir_intrinsic_load_streamout_offset_amd: case nir_intrinsic_load_task_ring_entry_amd: - case nir_intrinsic_load_task_ib_addr: - case nir_intrinsic_load_task_ib_stride: case nir_intrinsic_load_ring_attr_amd: case nir_intrinsic_load_ring_attr_offset_amd: case nir_intrinsic_load_sample_positions_pan: diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 4a172d0..3fecd17 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1394,9 +1394,6 @@ system_value("ring_mesh_scratch_amd", 4) system_value("ring_mesh_scratch_offset_amd", 1) # Pointer into the draw and payload rings system_value("task_ring_entry_amd", 1) -# Pointer into the draw and payload rings -system_value("task_ib_addr", 2) -system_value("task_ib_stride", 1) # Descriptor where NGG attributes are stored on GFX11. system_value("ring_attr_amd", 4) system_value("ring_attr_offset_amd", 1) -- 2.7.4