From b670dcb81b035babf92d8e6433d89c810ba97d59 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Fri, 3 Dec 2021 14:03:20 +0000 Subject: [PATCH] [AMDGPU] Add some more GFX10 test coverage --- llvm/test/CodeGen/AMDGPU/add.ll | 4 ++ llvm/test/CodeGen/AMDGPU/add.v2i16.ll | 62 ++++++++++++---------- .../CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll | 1 + 3 files changed, 39 insertions(+), 28 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/add.ll b/llvm/test/CodeGen/AMDGPU/add.ll index bce924e..112d788 100644 --- a/llvm/test/CodeGen/AMDGPU/add.ll +++ b/llvm/test/CodeGen/AMDGPU/add.ll @@ -1,6 +1,7 @@ ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,FUNC %s +; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,FUNC %s ; FUNC-LABEL: {{^}}s_add_i32: ; GCN: s_add_i32 s[[REG:[0-9]+]], {{s[0-9]+, s[0-9]+}} @@ -86,6 +87,7 @@ entry: ; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]] ; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, [[A]], [[B]] ; GFX9: v_add_u32_e32 v{{[0-9]+}}, [[A]], [[B]] +; GFX10: v_add_nc_u32_e32 v{{[0-9]+}}, [[A]], [[B]] define amdgpu_kernel void @v_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid @@ -101,6 +103,7 @@ define amdgpu_kernel void @v_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* % ; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] ; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, 0x7b, [[A]] ; GFX9: v_add_u32_e32 v{{[0-9]+}}, 0x7b, [[A]] +; GFX10: v_add_nc_u32_e32 v{{[0-9]+}}, 0x7b, [[A]] define amdgpu_kernel void @v_add_imm_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid @@ -166,6 +169,7 @@ endif: ; SI: v_add_i32_e64 v0, s[0:1], s0, v0 ; VI: v_add_u32_e64 v0, s[0:1], s0, v0 ; GFX9: v_add_u32_e32 v0, s0, v0 +; GFX10: v_add_nc_u32_e32 v0, s0, v0 ; GCN: ; def vcc ; GCN: ds_write_b32 diff --git a/llvm/test/CodeGen/AMDGPU/add.v2i16.ll b/llvm/test/CodeGen/AMDGPU/add.v2i16.ll index 42ea4b4..56e318c 100644 --- a/llvm/test/CodeGen/AMDGPU/add.v2i16.ll +++ b/llvm/test/CodeGen/AMDGPU/add.v2i16.ll @@ -1,9 +1,10 @@ -; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9PLUS,GFX9 %s +; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9PLUS,GFX10 %s ; FIXME: Need to handle non-uniform case for function below (load without gep). ; GCN-LABEL: {{^}}v_test_add_v2i16: -; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GFX9PLUS: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; FIXME: or should be unnecessary ; VI: v_add_u16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} @@ -22,10 +23,11 @@ define amdgpu_kernel void @v_test_add_v2i16(<2 x i16> addrspace(1)* %out, <2 x i } ; GCN-LABEL: {{^}}s_test_add_v2i16: -; GFX9: s_load_dword [[VAL0:s[0-9]+]] -; GFX9: s_load_dword [[VAL1:s[0-9]+]] +; GFX9PLUS: s_load_dword [[VAL0:s[0-9]+]] +; GFX9PLUS: s_load_dword [[VAL1:s[0-9]+]] ; GFX9: v_mov_b32_e32 [[VVAL1:v[0-9]+]] ; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VAL1]], [[VVAL1]] +; GFX10: v_pk_add_u16 v{{[0-9]+}}, [[VAL0]], [[VAL1]] ; VI: s_add_i32 ; VI: s_add_i32 @@ -38,8 +40,8 @@ define amdgpu_kernel void @s_test_add_v2i16(<2 x i16> addrspace(1)* %out, <2 x i } ; GCN-LABEL: {{^}}s_test_add_self_v2i16: -; GFX9: s_load_dword [[VAL:s[0-9]+]] -; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VAL]], [[VAL]] +; GFX9PLUS: s_load_dword [[VAL:s[0-9]+]] +; GFX9PLUS: v_pk_add_u16 v{{[0-9]+}}, [[VAL]], [[VAL]] ; VI: s_add_i32 ; VI: s_add_i32 @@ -53,6 +55,7 @@ define amdgpu_kernel void @s_test_add_self_v2i16(<2 x i16> addrspace(1)* %out, < ; FIXME: VI should not scalarize arg access. ; GCN-LABEL: {{^}}s_test_add_v2i16_kernarg: ; GFX9: v_pk_add_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} +; GFX10: v_pk_add_u16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; VI: s_add_i32 ; VI: s_add_i32 @@ -69,6 +72,7 @@ define amdgpu_kernel void @s_test_add_v2i16_kernarg(<2 x i16> addrspace(1)* %out ; GCN-LABEL: {{^}}v_test_add_v2i16_constant: ; GFX9: s_mov_b32 [[CONST:s[0-9]+]], 0x1c8007b{{$}} ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]] +; GFX10: v_pk_add_u16 v{{[0-9]+}}, 0x1c8007b, v{{[0-9]+}} ; VI-DAG: v_mov_b32_e32 v[[SCONST:[0-9]+]], 0x1c8 ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0x7b, v{{[0-9]+}} @@ -88,6 +92,7 @@ define amdgpu_kernel void @v_test_add_v2i16_constant(<2 x i16> addrspace(1)* %ou ; GCN-LABEL: {{^}}v_test_add_v2i16_neg_constant: ; GFX9: s_mov_b32 [[CONST:s[0-9]+]], 0xfc21fcb3{{$}} ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]] +; GFX10: v_pk_add_u16 v{{[0-9]+}}, 0xfc21fcb3, v{{[0-9]+}} ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0xfcb3, v{{[0-9]+}} ; VI-DAG: v_mov_b32_e32 v[[SCONST:[0-9]+]], 0xfffffc21 @@ -103,7 +108,7 @@ define amdgpu_kernel void @v_test_add_v2i16_neg_constant(<2 x i16> addrspace(1)* } ; GCN-LABEL: {{^}}v_test_add_v2i16_inline_neg1: -; GFX9: v_pk_sub_u16 v{{[0-9]+}}, v{{[0-9]+}}, 1 op_sel_hi:[1,0]{{$}} +; GFX9PLUS: v_pk_sub_u16 v{{[0-9]+}}, v{{[0-9]+}}, 1 op_sel_hi:[1,0]{{$}} ; VI-DAG: v_mov_b32_e32 v[[SCONST:[0-9]+]], -1 ; VI-DAG: flat_load_dword [[LOAD:v[0-9]+]] @@ -121,7 +126,7 @@ define amdgpu_kernel void @v_test_add_v2i16_inline_neg1(<2 x i16> addrspace(1)* } ; GCN-LABEL: {{^}}v_test_add_v2i16_inline_lo_zero_hi: -; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, 32{{$}} +; GFX9PLUS: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, 32{{$}} ; VI: flat_load_dword ; VI-NOT: v_add_u16 @@ -143,6 +148,7 @@ define amdgpu_kernel void @v_test_add_v2i16_inline_lo_zero_hi(<2 x i16> addrspac ; GCN-LABEL: {{^}}v_test_add_v2i16_inline_fp_split: ; GFX9: s_mov_b32 [[K:s[0-9]+]], 1.0 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]{{$}} +; GFX10: v_pk_add_u16 v{{[0-9]+}}, 0x3f80, v{{[0-9]+}} ; VI-NOT: v_add_u16 ; VI: v_mov_b32_e32 v[[K:[0-9]+]], 0x3f80 @@ -161,13 +167,13 @@ define amdgpu_kernel void @v_test_add_v2i16_inline_fp_split(<2 x i16> addrspace( ; FIXME: Need to handle non-uniform case for function below (load without gep). ; GCN-LABEL: {{^}}v_test_add_v2i16_zext_to_v2i32: -; GFX9: global_load_dword [[A:v[0-9]+]] -; GFX9: global_load_dword [[B:v[0-9]+]] +; GFX9PLUS: global_load_dword [[A:v[0-9]+]] +; GFX9PLUS: global_load_dword [[B:v[0-9]+]] -; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] -; GFX9-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]] -; GFX9-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] -; GFX9: buffer_store_dwordx2 v{{\[}}[[ELT0]]:[[ELT1]]{{\]}} +; GFX9PLUS: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] +; GFX9PLUS-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]] +; GFX9PLUS-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] +; GFX9PLUS: buffer_store_dwordx2 v{{\[}}[[ELT0]]:[[ELT1]]{{\]}} ; VI: flat_load_dword v[[A:[0-9]+]] ; VI: flat_load_dword v[[B:[0-9]+]] @@ -194,13 +200,13 @@ define amdgpu_kernel void @v_test_add_v2i16_zext_to_v2i32(<2 x i32> addrspace(1) ; FIXME: Need to handle non-uniform case for function below (load without gep). ; GCN-LABEL: {{^}}v_test_add_v2i16_zext_to_v2i64: -; GFX9: global_load_dword [[A:v[0-9]+]] -; GFX9: global_load_dword [[B:v[0-9]+]] +; GFX9PLUS: global_load_dword [[A:v[0-9]+]] +; GFX9PLUS: global_load_dword [[B:v[0-9]+]] -; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] -; GFX9-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]] -; GFX9-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] -; GFX9: buffer_store_dwordx4 +; GFX9PLUS: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] +; GFX9PLUS-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]] +; GFX9PLUS-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] +; GFX9PLUS: buffer_store_dwordx4 ; VI-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} ; VI-DAG: flat_load_dword v[[A:[0-9]+]] @@ -225,13 +231,13 @@ define amdgpu_kernel void @v_test_add_v2i16_zext_to_v2i64(<2 x i64> addrspace(1) ; FIXME: Need to handle non-uniform case for function below (load without gep). ; GCN-LABEL: {{^}}v_test_add_v2i16_sext_to_v2i32: -; GFX9: global_load_dword [[A:v[0-9]+]] -; GFX9: global_load_dword [[B:v[0-9]+]] +; GFX9PLUS: global_load_dword [[A:v[0-9]+]] +; GFX9PLUS: global_load_dword [[B:v[0-9]+]] -; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] -; GFX9-DAG: v_bfe_i32 v[[ELT0:[0-9]+]], [[ADD]], 0, 16 -; GFX9-DAG: v_ashrrev_i32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] -; GFX9: buffer_store_dwordx2 v{{\[}}[[ELT0]]:[[ELT1]]{{\]}} +; GFX9PLUS: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] +; GFX9PLUS-DAG: v_bfe_i32 v[[ELT0:[0-9]+]], [[ADD]], 0, 16 +; GFX9PLUS-DAG: v_ashrrev_i32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] +; GFX9PLUS: buffer_store_dwordx2 v{{\[}}[[ELT0]]:[[ELT1]]{{\]}} ; VI: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI: v_add_u16_e32 @@ -257,8 +263,8 @@ define amdgpu_kernel void @v_test_add_v2i16_sext_to_v2i32(<2 x i32> addrspace(1) ; GCN: {{flat|global}}_load_dword ; GCN: {{flat|global}}_load_dword -; GFX9: v_pk_add_u16 -; GFX9: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} +; GFX9PLUS: v_pk_add_u16 +; GFX9PLUS: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} ; VI: v_add_u16_sdwa ; VI: v_add_u16_e32 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll index 3c66f6e..c65c549 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1032 %s +; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1064 %s ; GCN-LABEL: {{^}}test_init_exec: ; GFX1032: s_mov_b32 exec_lo, 0x12345 -- 2.7.4