From b65ebb7573e74ec98ca5cfc0bf0850f927d43d1f Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Thu, 24 Jul 2014 13:57:19 +0100 Subject: [PATCH] drm: hdlcd: Add debugfs entry for displaying current pixelclock value When asking the hardware to set a new pixelclock value we might timeout on values that are calculated during request and not wait for the actual outcome of the clock setting. SCP could still finish the brute force search for the best PLL settings and might or might not set the requested resolution. To help track the current value of the pixelclock, add a new entry in debugfs that displays the HW programmed value vs the one that was requested for the current running mode. Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/hdlcd_drv.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c index e00f9d73e4b..1cbb7da9042 100644 --- a/drivers/gpu/drm/arm/hdlcd_drv.c +++ b/drivers/gpu/drm/arm/hdlcd_drv.c @@ -310,8 +310,22 @@ static int hdlcd_show_underrun_count(struct seq_file *m, void *arg) return 0; } +static int hdlcd_show_pxlclock(struct seq_file *m, void **arg) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct hdlcd_drm_private *hdlcd = dev->dev_private; + unsigned long clkrate = clk_get_rate(hdlcd->clk); + unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000; + + seq_printf(m, "hw : %lu\n", clkrate); + seq_printf(m, "mode: %lu\n", mode_clock); + return 0; +} + static struct drm_info_list hdlcd_debugfs_list[] = { { "interrupt_count", hdlcd_show_underrun_count, 0 }, + { "clocks", hdlcd_show_pxlclock, 0 }, }; static int hdlcd_debugfs_init(struct drm_minor *minor) -- 2.34.1