From b648d6fbf8c692fda62d40883d7bdc646cdab5ec Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 24 Aug 2021 11:29:31 -0400 Subject: [PATCH] radeonsi: disable DCC stores on Navi12-14 for displayable DCC to fix corruption This is a hardware limitation. Fixes: 1d64a1045ea205ee0 "radeonsi: enable dcc image stores on gfx10+" Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_descriptors.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 77bb136..e97d290 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -360,7 +360,10 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) | S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8) | - S_00A018_WRITE_COMPRESS_ENABLE((access & SI_IMAGE_ACCESS_DCC_WRITE) != 0); + /* DCC image stores require INDEPENDENT_128B_BLOCKS, which is not set + * with displayable DCC on Navi12-14 due to DCN limitations. */ + S_00A018_WRITE_COMPRESS_ENABLE(tex->surface.u.gfx9.color.dcc.independent_128B_blocks && + access & SI_IMAGE_ACCESS_DCC_WRITE); } state[7] = meta_va >> 16; -- 2.7.4