From b608a89221b401d7b07a1b6330777a034d204410 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 6 Jun 2017 12:45:54 -0300 Subject: [PATCH] clk: imx7d: Fix the DDR PLL enable bit Commit ad14972422899b6 ("clk: imx7d: Fix the powerdown bit location of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case. Fix it accordingly to avoid a kernel hang. Reported-by: Leonard Crestez Signed-off-by: Fabio Estevam Reviewed-by: Stefan Agner Signed-off-by: Stephen Boyd --- drivers/clk/imx/clk-pllv3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 0039b16..9af62ee 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -453,7 +453,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, ops = &clk_pllv3_enet_ops; break; case IMX_PLLV3_DDR_IMX7: - pll->power_bit = IMX7_ENET_PLL_POWER; + pll->power_bit = IMX7_DDR_PLL_POWER; ops = &clk_pllv3_av_ops; break; default: -- 2.7.4